The use of conventional thermally cross-linked materials in advanced lithography and nano-imprinting techniques, such
as negative photo resist, anti reflective coatings and planarizing layers, does not guarantee that a high degree of
planarization will be obtained. Additionally, iso-dense thickness biases can create problems by narrowing process
This presentation focuses on the correlation between simulated and experimental analyses and how planarization is
affected. The factors we have identified that influence a material's planarizing capability are; coating spin speed, spin
time and the relationship between the solvent concentration of the material and it's via filling properties. Through
optimization of these factors, an appreciable reduction in via topography was achieved. Based on our results, novel, UV
cross-linkable materials have been developed and optimized for improving planarity in via applications.
193nm immersion and Hyper NA lithography are used at 45nm and beyond. The next generation of lithography will use a new technology such as Double Pattering, EUV or EB. Double patterning is one of the currently acceptable technologies.
Three common double pattern techniques are Litho-Etch-Litho-Etch (LELE), freezing, and sidewall (spacer) process. From a technical standpoint LELE is a very promising process, except for the second litho alignment. However, the cost of ownership will be very high because LELE will cost about twice as much as the current single litho patterning process. In order to build up a suitable double patterning technique, many device makers are developing unique processes. Two of these processes are freezing and sidewall. Flash memory makers are diligently investigating the sidewall process by CVD. This is because of the lack of a second litho alignment step, even with its high cost. The high cost of the CVD process can be reduced if a spin on material is used.
One of the goals of this paper is to reduce the cost of ownership by using spin on coatings for the sidewall process. Currently we are investigating this approach to control the sidewall width, profile and other properties.