The objective of this paper is to extend the ability of a more stable overall process control for the 28 nm Metal layer. A method to better control complex 2D-layout structures for this node is described. Challenges are coming from the fact that the structures, which limit the process window are mainly of 2D routing nature and are difficult to monitor. Within the framework of this study the emphasis is on how to predict these process-window-limiting structures upfront, to identify root causes and to assist in easier monitoring solutions enhancing the process control. To address those challenges, the first step is the construction of a reliable Mask-3D and Resist-3D model. Advanced 3Dmodeling allows better prediction of process variation upfront. Furthermore it allows highlighting critical structures impacted by either best-focus shifts or by low-contrast resist-imaging effects, which then will be transferred non-linearly after etch. This paper has a tight attention on measuring the 3D nature of the resist profiles by multiple experimental techniques such as Cross-section scanning electron microscopy methods (X-SEM) and atomic force microscopy (AFM). Based on these measurements the most reliable data are selected to calibrate full-chip Resist-3D model with. Current results show efficient profile matching among the calibrated R3D model, wafer AFM and X-SEM measurements. In parallel this study enables the application of a new metric as result of the resist profiles behavior in function of exposure dose. In addition it renders the importance on the resist shape. Together these items are reflected to be efficient support on process optimization and improvement on the process control.
At the 20nm technology node, it is challenging for simple resolution enhancements techniques (RET) to achieve sufficient process margin due to significant coupling effects for dense features. Advanced computational lithography techniques including Source Mask Optimization (SMO), thick mask modeling (M3D), Model Based Sub Resolution Assist Features (MB-SRAF) and Process Window Solver (PW Solver) methods are now required in the mask correction processes to achieve optimal lithographic goals. An OPC solution must not only converge to a nominal condition with high fidelity, but also provide this fidelity over an acceptable process window condition. The solution must also be sufficiently robust to account for potential scanner or OPC model tuning. In many cases, it is observed that with even a small change in OPC parameters, the mask correction could have a big change, therefore making OPC optimization quite challenging. On top of this, different patterns may have significantly different optimum source maps and different optimum OPC solution paths. Consequently, the need for finding a globally optimal OPC solution becomes important. In this work, we introduce a holistic solution including source and mask optimization (SMO), MB-SRAF, conventional OPC and Co-Optimization OPC, in which each technique plays a unique role in process window enhancement: SMO optimizes the source to find the best source solution for all critical patterns; Co-Optimization provides the optimized location and size of scattering bars and guides the optimized OPC solution; MB-SRAF and MB-OPC then utilizes all information from advanced solvers and performs a globally optimized production solution.
From 28 nm technology node and below optical proximity correction (OPC) needs to
take into account light scattering effects from prior layers when bottom anti-reflective coating
(BARC) is not used, which is typical for ionic implantation layers. These effects are complex,
especially when multiple sub layers have to be considered: for instance active and poly structures
need to be accounted for.
A new model form has been developed to address this wafer topography during model
calibration called the wafer 3D+ or W3D+ model. This model can then be used in verification
(using Tachyon LMC) and during model based OPC to increase the accuracy of mask correction
and verification. This paper discusses an exploration of this new model results using extended
wafer measurements (including SEM). Current results show good accuracy on various
In previous work1, we introduced a new technology called Flexible Mask Optimization (FMO) that was successfully used for localized OPC correction. OPC/RET techniques such as model-based assist feature and process-window-based OPC solvers have become essential for addressing critical patterning issues at 2× and lower technology nodes. With an FMO flow, critical patterns were identified, classified and corrected in localized areas only, using advanced techniques. One challenge with this flow is that once the hotspots are identified, a user still has to come up with OPC solutions to address the hotspots. This process can be cumbersome and time consuming as different types of hotspots with new designs may require different recipes, causing delays to tapeout. What is required is a robust, powerful and automated OPC technique that can handle various types of hotspots, so an automatic hotspot correction flow can be established. In this work, we introduce a new cost-function-based OPC technique called Co-optimization OPC that can be used to correct various types of hotspots with minimum tuning effort. In this approach, the OPC solver simultaneously solves for all the segments in a patch including main and sub-resolution assist features (SRAF), applying additional user-defined cost function constraints such as MEEF, PV band, MRC and SRAF printability. Unlike conventional OPC solvers, Cooptimization solvers can also move and grow SRAFs, which further improves the process window. The key benefit of the Co-optimization OPC solution is that it can be used in a standard recipe to resolve many different hotspots encountered across various designs for a given layer. In this study, we demonstrate that Co-optimization OPC can be successfully used to address various types of hotspots across designs for selected 2× nm node line/space layers, as an example. These layers have been particularly challenging as they use single-exposure lithography with k1 around 0.3. Aggressive RET solutions are required to address the patterning challenges for this layer. Finally, we will report on implementation of the Co-Optimization OPC Recipe within the FMO framework for hotspot correction.
As the semiconductor industry moves to double patterning solutions for smaller feature sizes,
photolithography simulators will be required to model the effects of non-planar film stacks in the
lithography process. This presents new computational challenges for modeling the exposure, post-exposure
bake (PEB), and development steps. The algorithms are more complex, sometimes requiring very different
formulations than in the all-planar film stack case. It is important that the level of accuracy of the models
For these reasons, we have extended our previous papers in which we proposed standard benchmark
problems for computations such as rigorous EMF mask diffraction, optical imaging, PEB, and development
[1-4]. In this paper, we evaluate the accuracy of the new PROLITH wafer topography models. The
benchmarks presented here pertain to the models (and their associated outputs) most affected by the switch
to non-planar film stacks: imaging at the wafer (image intensity in-media) and PEB (blocked polymer
concentration). Closed-form solutions are formulated with the same assumptions used in the model
implementation. These solutions can be used as an absolute standard and compared against a simulator. The
benchmark can then be used to judge the simulator, in particular as it applies to speed vs. accuracy
Beyond 40nm lithography node, mask topograpy is important in litho process. The rigorous EMF simulation should
be applied but cost huge time. In this work, we compared experiment data with aerial images of thin and thick mask
models to find patterns which are sensitive to mask topological effects and need rigorous EMF simulations. Furthur more,
full physical and simplified lumped (LPM) resist models were calibrated for both 2D and 3D mask models. The accuracy
of CD prediction and run-time are listed to gauge the most efficient simulation. Although a full physical resist model
mimics the behavior of a resist material with rigor, the required iterative calculations can result in an excessive execution
time penalty, even when simulating a simple pattern. Simplified resist models provide a compromise between
computational speed and accuracy.
The most efficient simulation approach (i.e. accurate prediction of wafer results with minimum execution time) will
have an important position in mask 3D simulation.
Line/space dimensions for 22nm logic are expected to be ~35nm at ~70nm pitch for metal 1. However, the contacted
gate pitch will be ~90nm because of contact-to-gate spacing limited by alignment. A process for self-aligning contact to
gates and diffusions could reduce the gate pitch and hence directly reduce logic and memory cells sizes.
Self-aligned processes have been in use for many years. DRAMs have had bit-line and storage-node contacts defined in
the critical direction by the row-lines. More recently, intra-layer self-alignment has been introduced with spacer double
patterning, in which pitch division is accomplished using sidewall spacers defined by a removable core. This
approach has been extended with pitch division by 4 to the 7nm node.
The introduction of logic design styles which use strictly one-directional lines for the critical levels gives the opportunity
for extending self-alignment to inter-layer applications in logic and SRAMs. Although Gridded Design Rules have been
demonstrated to give area-competitive layouts at existing 90, 65, and 45nm logic nodes while reducing CD
variability, process extensions are required at advanced nodes like 22nm to take full advantage of the regular layouts.
An inter-layer self-aligning process has been demonstrated with both simulations and short-loop wafers. An extension of
the critical illumination step for active and gate contacts will be described.
Recent publications have emphasized the criticality of computational lithography in source-mask selection for 32 and 22
nm technology nodes. Lithographers often select the illuminator geometries based on analyzing aerial images for a
limited set of structures using computational lithography tools. Last year, Biafore, et al1 demonstrated the divergence
between aerial image models and resist models in computational lithography. In a follow-up study2, it was illustrated that
optimal illuminator is different when selected based on resist model in contrast to aerial image model. In the study,
optimal source shapes were evaluated for 1D logic patterns using aerial image model and two distinct commercial resist
models. Physics based lumped parameter resist model (LPM) was used. Accurately calibrated full physical models are
portable across imaging conditions compared to the lumped models. This study will be an extension of previous work.
Full physical resist models (FPM) with calibrated resist parameters3,4,5,6 will be used in selecting optimum illumination
geometries for 1D logic patterns. Several imaging parameters - like Numerical Aperture (NA), source geometries
(Annular, Quadrupole, etc.), illumination configurations for different sizes and pitches will be explored in the study. Our
goal is to compare and analyze the optimal source-shapes across various imaging conditions. In the end, the optimal
source-mask solution for given set of designs based on all the models will be recommended.
It is common for computational lithography optimization to be performed using the metrics of the
simulated aerial image (AI). Using the AI, the wafer-level CD can be estimated in a number of ways, such
as thresholding with or without convolution of the AI with a point-spread function. The assumption of such
an approach is that the relationship between the AI CD and the resist CD response is linear. However, the
properties of resist reaction-diffusion-development yield a process which is highly non-linear. For example,
it is well-known that different photoresists produce a different lithographic response to the same aerial
image; isofocality, depth-of-focus, exposure latitude, MEF etc. all vary from one resist to another for the
same projection optics and mask. Several publications have demonstrated that a well-calibrated physical
resist model can be extrapolated to accurately predict the CD and profile response of the resist process over
a wide range of optical and process conditions1-4. In this work, the divergence in performance between
resist processes and the projected image-in-the resist is explored through simulation.
The RET selection process, for 32 nm and 22 nm technology nodes, is becoming evermore complex due to an increase in
the availability of strong resolution enhancements (e.g., polarization control, custom exotic illuminators, hyper NA).
Lithographers often select the illuminator geometries based on analyzing aerial images for a limited set of structures.
However, source-shape geometries optimized using this methodology is not always optimal for other complex patterns.
This leads to critical hot-spots on the final wafer images in form of bridges and gaps. Lithographers would like to
analyze the impact of selected source-shape on wafer results for the complex patterns before running the physical
experiments. Physics based computational lithography tools allow users to predict the accurate wafer images. This
approach allows users to run large factorial experiments for simple and complex designs without running physical
experiments. In this study, we will analyze the lithographic performance of simple 1D patterns using aerial image models
and physical resist models with calibrated resist parameters1,2,3,4 for two commercial resists. Our goal is to determine
whether physical resist models yield a different optimal solution as compared to the aerial image model. We will explore
several imaging parameters - like Numerical Aperture (NA), source geometries (Annular, Quadrupole, etc.), illumination
configurations and anchor features for different sizes and pitches. We will apply physics based OPC and compute
common process windows using physical model. In the end, we will analyze and recommend the optimal source-mask
solution for given set of designs based on all the models.
It is common for computational lithography optimization to be performed using the metrics of the simulated aerial image (AI). Using the AI, the wafer-level CD can be estimated in a number of ways, such as thresholding with or without convolution of the AI with a point-spread function. The assumption of such an approach is that the relationship between the AI CD and the resist CD response is linear. However, the properties of resist reaction-diffusion-development yield a process which is highly non-linear. For example, it is well-known that different photoresists produce a different lithographic response to the same aerial image; isofocality, depth-of-focus, exposure latitude, MEF etc. all vary from one resist to another for the same projection optics and mask. Several publications have demonstrated that a well-calibrated physical resist model can be extrapolated to accurately predict the CD and profile response of the resist process over a wide range of optical and process conditions. In this work, the divergence in performance between resist processes and the projected image-in-the resist is explored through simulation.
Over the past several years, choosing the best Resolution Enhancement Technique (RET) has become more and
more difficult. The RET implementation team is faced with an ever increasing number of variables to attempt to
optimize. Also, for a given node, there are now more layers designated as critical pattern layers requiring RET. As
design rules become more aggressive, and scanners have more process parameters such as polarization and focus
drilling, RET must be optimized across a larger number of variables than before. Sorting through the best combination of
all of the available process parameters could potentially require the number of wafer experiments to increase
exponentially. Rigorous, physics-based computational lithography is the perfect tool for executing the large number of
experiments, virtually, culling out dramatically the actual number of physical wafer experiments required for
verification. Ideally, first pass RET selection needs to be made as early as possible in the technology cycle, well before
the equipment is available. Traditional OPC tools, which require wafer process data to set up are not suited to this task,
as they can only be used after the equipment has been installed and a stable, established process exists. Rigorous physical
and chemical models, such as those found in PROLITH, are better suited to early RET selection and optimization but the
Windows platform, where PROLITH is used, is computationally too slow for the massive number of calculations
required. In this study, we focus on the RET selection process for a set of "typical" critical test patterns, using KLATencor's
other rigorous, physics-based computational lithography tool, LithoWare. LithoWare combines the accuracy of
rigorous physical and chemical models with the computational power of distributed computing on Linux. We examine
the use of cluster computing in optimizing the illuminators using model based OPC and process window analysis for
critical contact hole (CH) patterns. We use the results to propose a comprehensive RET selection strategy to meet the
user requirements of 45nm and 32 nm development.
Horizontal-Vertical (H-V) bias is the systematic difference in linewidth between closely located
horizontally and vertically oriented resist features that, other than orientation, should be
identical. There are two major causes of H-V bias: astigmatism, which causes an H-V bias that
varies through focus, and illumination source errors such as telecentricity error. In this paper,
the effects of simple dipole source errors upon H-V bias and placement error through focus are
explored through simulation.