In this work, a study of two different types of current aperture vertical electron transistor (CAVET) with ion-implanted blocking layer are presented. The device fabrication and performance limitation of a CAVET with a dielectric gate is discussed, and the breakdown limiting structure is evaluated using on-wafer test structures. The gate dielectric limited the device breakdown to 50V, while the blocking layer was able to withstand over 400V. To improve the device performance, an alternative CAVET structure with a p-GaN gate instead of dielectric is designed and realized. The pGaN gated CAVET structure increased the breakdown voltage to over 400V. Measurement of test structures on the wafer showed the breakdown was limited by the blocking layer instead of the gate p-n junction.
Al2O3 has been an attractive gate dielectric for GaN power devices owing to its large conduction band offset with GaN (~2.13eV), relatively high dielectric constant (~9.0) and high breakdown electric field (~10 MV/cm). Due to exceptional control over film uniformity and deposition rate, atomic layer deposition (ALD) has been widely used for Al2O3 deposition. The major obstacle to ALD Al2O3 on GaN is its high interface-state density (Dit) caused by incomplete chemical bonds, native oxide layer and impurities at the Al2O3/GaN interface. Therefore, an appropriate surface pretreatment prior to deposition is essential for obtaining high-quality interface. In this study, we investigated the effect of TMA, H2O and Ar/N2 plasma pretreatment on Dit and border traps (Nbt). 5 cycles of TMA purge, 5 cycles of H2O purge and Ar/N2 plasma pretreatment were conducted on GaN prior to deposition of ALD Al2O3. Al2O3/GaN metaloxide-semiconductor capacitors (MOSCAPs) were fabricated for the characterization of Dit and Nbt using UV-assisted capacitance-voltage (C-V) technique. The results show that TMA and H2O pretreatment had trivial effects on interface engineering whereas Ar/N2 plasma pretreatment slightly reduced Dit and significantly reduced Nbt.