As technology nodes scale beyond 20nm node, design complexity increases and printability issues become more critical and hard for RET techniques to fix. It is now mandatory for designers to run lithography checks prior to tape out and acceptance by the foundry. As lithography compliance became a sign-off criterion, lithography hotspots are increasingly treated like DRC violations. In the case of lithography hotspot, layout edges that should be moved to fix the hotspot are not necessarily the edges directly touching it. As a result of that, providing the designer with a suggested layout movements to fix the lithography hotspot is becoming a necessity. Software solutions generating hints should be accurate and fast. In this paper we are presenting a methodology for providing hints to the designers to fix Litho-hotspots in the 20nm and beyond.
The need to quickly and flexibly characterize the design manufacturability increases as circuit design scales beyond the
22nm node. Improvements in design practices and design software are enabling this process. The use of carefully
characterized design subunits (cells) in the general assembly of the chip is one way to ensure that products are optimized
for these increasingly difficult lithographic process challenges. Additionally, software for assessing design robustness
has been enhanced to deal with ever more complex resolution enhancement techniques. State of the art simulator and
verification tool sets provide the necessary step of creating simulation contours and process variability bands upon which
various checks can then be performed. The construction of these contours and bands is often hidden from the user as traditional single or double exposure processes of one or two masks are assumed to be used to create the final layout pattern.