As we presented in the last conference, it is much difficult to get down the k1 limit of EUV lithography compared to that of optical lithography especially recent immersion lithography. Even though current 0.33NA NXE3300 tool has enhanced aberration characteristics and variable illumination mode than its predecessor, ADT and NXE3100, still there are limitations related with resolution capability of EUV lithography. First of all, photon shot noise and immature resist performances play an important role in patterning of very fine patterns. As already known, low sensitivity resists have been widely used to reduce shot noise. However, when considering productivity in EUV lithography, high sensitivity resists are inevitable, so it is necessary to increase image contrast by reducing scanner blur like aberration, M3D, stray light et al. We have investigated the impact of aberration and limitation in illumination pupil fill ratio in EUV. In particular, the aberration sensitivity is different by the illumination conditions, this was intensified when using the particular pupil. Because the lens calibration is conducted with standard illumination condition in NXE3300, it is necessary to consider different aberration sensitivity in accordance with pattern and used pupil condition in EUV lithography. To ensure the process margin of tech node close to limit, a flexpupil with low pupil fill ratio (PFR) than 0.2 were required. Hence in order to avoid through-put loss at this condition, the new concept of the illuminator design is required without light loss. Contamination of collector mirror can affect the patterning also. We will also report about the patterning effect of pupil deformation by degraded collector in low PFR condition.
The improvement of overlay control in extreme ultra-violet (EUV) lithography is one of critical issues for successful mass production by using it. Especially it is important to improve the mix and match overlay or matched machine overlay (MMO) between EUV and ArF immersion tool, because EUV process will be applied to specific layers that have more competitive cost edge against ArF immersion multiple patterning with the early mass productivity of EUVL. Therefore it is necessary to consider the EUV overlay target with comparing the overlay specification of double patterning technology (DPT) and spacer patterning technology (SPT). This paper will discuss about required overlay controllability and current performance of EUV, and challenges for future improvement.
Sub 0.3k1 regime has been widely adopted for high volume manufacturing (HVM) of optical lithography due to various resolution enhancement technologies (RETs). It is not certain when such low k1 is feasible in EUV, though most technologies are available in EUV also. In this paper, experimental results on patterning performance of line space (L/S) and contact hole (C/H) in EUV lithography will be presented. First, practical k1 value with 0.33NA EUV lithography was investigated through experiment using NXE3300 EUV tool. Patterning limit, as defined by local critical dimension uniformity (LCDU) for C/H array pattern were measured with respect to various design rules. It was evaluated that the effect of off axis illumination (OAI) mode with various illumination conditions to improve the patterning performance and to reduce k1 limit. Then the experimental results of LCDU were compared with normalized image log slope (NILS) values from simulation. EUV source mask optimization (SMO) technologies to increase NILS with FlexPupil option of EUV scanner were evaluated and possibility of further improvement was also discussed.
In this paper, we will present the experimental comparison results on contact holes (CHs) and pillars patterning in EUV lithography with several candidate processes. Firstly, we have compared the normalized image log-slope (NILS), local critical dimension uniformity (LCDU) and dose-to-size (DtS) with respect to positive tone imaging (PTI) and negative tone imaging (NTI) process by EUV stochastic simulation. From the simulation results, we found that NTI process has higher absorbed photon density that can reduce the DtS and the LCDU of pillars pattern is improved with higher NILS compared to CHs patterning with similar DtS. So we have experimentally evaluated the pillars patterning process with 0.25NA EUV scanner system and compared the process margin, LCDU and DtS with the same parameters of the CHs pattering process. Further, we have demonstrated the CHs patterning with reverse process from pillars by using the dry development rinse process (DDRP). Different to the simulation results, the experimental LCDU results of pillars pattern and CHs pattern by DDRP show worse values comparing with the reference resist CHs pattern. In order to analyze these results, we have investigated the effect of flare, target CD, PR thickness and mask stack of the experimental conditions. Furthermore, we have evaluated the pillar patterning with NTD resist and by DDRP.
Overlay performance will be increasingly important for Spacer Patterning Technology (SPT) and Double Patterning
Technology (DPT) as various Resolution Enhancement Techniques are employed to extend the resolution limits of
lithography. Continuous shrinkage of devices makes overlay accuracy one of the most critical issues while overlay
performance is completely dependent on exposure tool.
Image Based Overlay (IBO) has been used as the mainstream metrology for overlay by the main memory IC companies,
but IBO is not suitable for some critical layers due to the poor Tool Induced Shift (TIS) values. Hence new overlay
metrology is required to improve the overlay measurement accuracy. Diffraction Based Overlay (DBO) is regarded to
be an alternative metrology to IBO for more accurate measurements and reduction of reading errors. Good overlay
performances of DBO have been reported in many articles. However applying DBO for SPT and DPT layers poses
extra challenges for target design. New vernier designs are considered for different DPT and SPT schemes to meet
overlay target in DBO system.
In this paper, we optimize the design of the DBO target and the performance of DBO to meet the overlay specification
of sub-3x nm devices which are using SPT and DPT processes. We show that the appropriate vernier design yields
excellent overlay performance in residual and TIS. The paper also demonstrated the effects of vernier structure on
overlay accuracy from SEM analysis.
In recent years, DRAM technology node has shrunk below to 40nm HP (Half Pitch) patterning with significant
progresses of hyper NA (Numerical Aperture) immersion lithography system and process development. Especially, the
development of DPT (Double Patterning Technology) and SPT (Spacer Patterning Technology) can extend the resolution
limit of lithography to sub 30nm HP patterning. However it is also necessary to improve the tighter overlay control for
developing the sub 40nm DRAM because of small device overlap margin. Since new process technologies such as
complex structure of DPT and SPT, new hard mask material and extreme CMP (Chemical Mechanical Planarization)
process have also applied as design rule is decreased, the improvement of process overlay control is very important.
In this paper, we have studied that the characterization of overlay performance for sub 40nm DRAM with actual
experimental data. First, we have investigated the influence on the intra field overlay and inter field overlay with
comparison of HOWA and HOPC and the improvement of inter field overlay residual errors. Then we have studied the
process effects such as hard mask material, thermal process and CMP process that affect to overlay control.
In this paper, we will present applications of MoSi-based binary intensity mask for sub-40nm DRAM with hyper-NA
immersion scanner which has been the main stream of DRAM lithography. Some technical issues will be reported for
polarized illumination and mask materials in hyper-NA imaging. One att.PSM (Phase Shift Mask) and three types of
binary intensity mask are used for this experiment; those are ArF att.PSM ( MoSi:760Å , transmittance 6% ),
conventional Cr ( 1030Å ) BIM (Binary Intensity Mask), MoSi-based BIM ( MoSi:590Å , transmittance 0.1%) and multi
layer ( Cr:740Å / MoSi:930Å ) BIM. Simulation and experiment with 1.35NA immersion scanner are performed to study
influence of mask structure, process margin and effect of polarization. Two types of DRAM cell patterns are studied; one
is a line and space pattern and the other is a contact hole pattern through mask structure. Various line and space pattern is
also through 38nm to 50nm half pitch studied for this experiment. Lithography simulation is done by in-house tool based
on diffused aerial image model. EM-SUITE is also used in order to study the influence of mask structure and
polarization effect through rigorous EMF simulation. Transmission and polarization effects of zero and the first
diffraction orders are simulated for both att.PSM and BIM. First and zero diffraction order polarization are shown to be
influenced by the structure of masking film. As pattern size on mask decreases to the level of exposure wavelength,
incident light will interact with mask pattern, thereby transmittance changes for mask structure. Optimum mask bias is
one of the important factors for lithographic performance. In the case of att.PSM, negative bias shows higher image
contrast than positive one, but in the case of binary intensity mask, positive bias shows better performance than negative
one. This is caused by balance of amplitude between first diffraction order and zero diffraction order light.1
Process windows and mask error enhancement factors are measured with respect to several types of mask structure. In
the case of one dimensional line and space pattern, MoSi-based BIM and conventional Cr BIM show the best
performance through various pitches. But in the case of hole DRAM cell pattern, it is difficult to find out the advantage
of BIM except of exposure energy difference. Finally, it was observed that MoSi-based binary intensity mask for sub-
40nm DRAM has advantage for one dimensional line and space pattern.
In this paper, we will present comparison of DRAM cell patterning between ArF immersion and EUV lithography which
will be the main stream of DRAM lithography. Assuming that the limit of ArF immersion single patterning is around
40nm half pitch, EUV technology is positioned on essential stage because development stage of device manufacturer is
going down sub-40nm technology node. Currently lithography technology, in order to improve the limitation of ArF
immersion lithography, double patterning technology (DPT) and spacer patterning technology (SPT) have been
examined intensively. However, double patterning and spacer patterning technology are not cost-effective process
because of complexity of lithography process such as many hard mask stacks and iterative litho, etch process. Therefore,
lithography community is looking forward to improving maturity of EUVL technology.
In order to overcome several issues on EUV technology, many studies are needed for device application. EUV
technology is different characteristics with conventional optical lithography which are non-telecentricity and mask
topography effect on printing performance. The printed feature of EUV is shifted and biased on the wafer because of
oblique illumination of the mask. Consequently, target CD and pattern position are changed in accordance with pattern
direction, pattern type and slit position of target pattern.1
For this study, we make sub-40nm DRAM mask for ArF immersion and EUV lithography. ArF attenuated PSM (Phase
Shift Mask) and EUV mask (LTEM) are used for this experiment; those are made and developed by in-house captive
maskshop. Simulation and experiment with 1.35NA ArF immersion scanner and 0.25NA EUV full field scanner are
performed to characterize EUV lithography and to compare process margin of each DRAM cell. Two types of DRAM
cell patterns are studied; one is an isolation pattern with a brick wall shape and another is a storage node pattern with
contact hole shape. Line and space pattern is also studied through 24nm to 50nm half pitch for this experiment.
Lithography simulation is done by in-house tool based on diffused aerial image model. EM-SUITE and Solid-EUV are
also used in order to study characteristics of EUV patterning through rigorous EMF simulation. We also investigated
shadowing effect according to pattern shape and design rule respectively. We find that vertical to horizontal bias is
around 2nm on 32nm to 40nm half pitch line and space pattern. In the case of DRAM cell, we also find same result with
line and space pattern. In view of mask-making consideration, we optimize absorber etch process. So we acquire vertical
absorber profile and mask MTT(Mean To Target) within 10% of target CD through several pitch.
Process windows and mask error enhancement factors are measured with respect to several DRAM cell pattern. In the
case of one dimensional line and space and two dimensional brick wall pattern, vertical pattern shows the best
performance through various pitches because of lower shadowing effect than horizontal pattern. But in case of contact hole DRAM cell pattern such as storage node pattern, it has bigger MEF value than one or two dimensional pattern
because of independency of shadowing effect. Finally, we compare with 2x, 3x and 4x DRAM cell patterning
performance in terms of pattern fidelity, slit CD uniformity and shadowing effect.
In the field of lithography technology, EUV lithography can be a leading candidate for sub-30 nm technology node.
EUVL expose system has different characteristics compared to DUV exposure system. EUV source wavelength is short
and no material is transparent to the source. So off-axis reflective optic system is used for patterning in place of on-axis
refractive system of DUV system. And different reticle design is needed that consists of 40 pair of Mo/Si multi layer
and absorber layer in place of conventional mask. Because of the oblique incidence on the mask, shadowing effect is
occurred such as pattern asymmetry, shift and pattern bias depending on pattern orientation. For non-telecentric
characteristics of EUV scanner, shadowing effect produces CD variation versus field position. Besides, it is well
known that EUV scanner has bigger flare than conventional DUV scanner. Therefore, the correction of mask shadowing
effect and flare level are one of the important issues for EUV lithography.
In this paper, process window and MEF of EUV lithography has been examined by 3D mask simulation. CD
variation by shadowing is simulated for various pattern orientations. A shadowing correction method has been
calculated due to field position to reduce shadowing effect. And the correction effect is examined by simulation and
Experimental results. Principle of radial overlay shift due to field position is verified then the shift length of line and
space pattern is calculated.
In this paper, we will present experimental results on sub-40nm node patterning of DRAM and some technical issues for capping freezing in simplified double patterning lithography. Lithography resolution limit of single pattern is 40nm in ArF immersion process. For sub-40nm patterning, we have to use double patterning lithography or EUV process. But, double patterning lithography process is very complicated and expensive solution. And EUV volume production technology will be not ready until 2012. Therefore, we have tried a simplified double patterning lithography.
In recent years, DRAM and Flash technology node has shrunk below to 45nm half pitch (HP) patterning with significant progresses of hyper numerical aperture (NA) immersion lithography system and process development. Several technologies such as extreme ultra violet (EUV) lithography, double patterning technology (DPT) and spacer patterning technology (SPT) have been developed for sub 40nm HP device. High index immersion lithography (HIL) is also one of the candidates for next generation lithography technology that has benefits of product cost, process simplification and usage for existing infrastructure though this technology must overcome critical issues--high index immersion fluid and lens optic development.
In this paper, we will present simulation results on sub 40nm imaging characterization for HIL.
First, we have studied the image performance for sub 40nm patterning with HIL. The image contrast, optical proximity effect and mask error enhanced factor (MEEF) are investigated through simulation. As pattern size decrease and lens NA gets bigger and bigger, the features on mask get smaller even below the wavelength of light and polarization related effects become one of the most critical issues. From comparison with results for 45nm HP patterning, we are able to suggest the reasonable process condition for HIL process.
Then, we have investigated the optimum BARC condition to make preparations for 32nm HP pattering.
In this paper, we will present comparison of attenuated phase shift mask and binary intensity mask at hyper-NA
immersion scanner which has been the main stream of DRAM lithography. Some technical issues will be reported for
polarized illumination in hyper-NA imaging. One att.PSM (Phase Shift Mask) and three types of binary intensity mask
are used for this experiment; those are ArF att.PSM ( MoSi:Å ), thick Cr ( 1030Å ) BIM (Binary Intensity Mask),
thin Cr ( 590Å ) BIM and multi layer ( Cr:740Å / MoSi:930Å ) BIM. Simulation and experiment with 1.35NA
immersion scanner are performed to study influence of mask structure, process margin and effect of polarization. Two
types of DRAM cell patterns are studied; one is an isolation pattern with a brick wall shape and another is a storage node
pattern with contact hole shape. Line and space pattern is also studied through 38nm to 50nm half pitch for this
experiment. Lithography simulation is done by in-house tool based on diffused aerial image model. EM-SUITE is also
used in order to study the influence of mask structure and polarization effect through rigorous EMF simulation.
Transmission and polarization effects of zero and first diffraction order are simulated for both att.PSM and BIM. First
and zero diffraction order polarization are shown to be influenced by the structure of masking film. As pattern size on
mask decreases to the level of exposure wavelength, incident light will interact with mask pattern, and then transmittance
changes for mask structure. Optimum mask bias is one of the important factors for lithographic performance. In the case
of att.PSM, negative bias shows higher image contrast than positive one, but in case of binary intensity mask, positive
bias shows better performance than negative one. This is caused by balance of amplitude between first diffraction order
and zero diffraction order light.
Process windows and mask error enhancement factors are measured with respect to various design rules, i.e., different k1
levels at fixed NA. In the case of one dimensional line and space pattern, thick Cr BIM shows the best performance
through various pitches. But in case of two dimensional DRAM cell pattern, it is difficult to find out the advantage of
BIM for sub-45nm. It needs further study for two dimensional patterns. Finally, it was observed that thick Cr binary
intensity mask for sub-45nm has advantage for one dimensional line and space pattern.
Though immersion lithography is on the verge of starting mass-production, demerit in overlay controllability by
immersion is thought as one of last huddle for that. The first issue in immersion tool has not been matured compared to
dry tool. As design rule is getting smaller, overlay specification is also changing the same way. But immersion tool is
not ready to meet this tighter overlay specification. The second issue is regarding the material which is used for
immersion process: top coat and water. Process details of material are needed to be verified thoroughly about how each
parameter affect on alignment and overlay respectively. In this paper, we made a split experiment about machine
parameter and investigated top coat effect on overlay. To improve overlay performance of immersion, we analyzed
machine parameters: scan-speed, settling time, UPW(Ultra Pure Water) flow etc. And we made an experiment about
how the effect of top coat is appeared on overlay through simulation and experiment. In the experiments, we used
ASML 1400i scanner. Resolution improvement of immersion tool has been proved by lots of papers, but it is need to be
verified of overlay controllability that getting tighter. Continuously, we believe that most efforts are to be focused on
overlay control issue.
ArF Immersion lithography is expected to be a production-worthy technology for sub-60nm DRAM. It gives wider
process window and better CD uniformity at the cost of defects and overlay accuracy. It is generally mentioned that
immersion defects are generated during exposure and removed through pre-soak and post-soak process. A lot of efforts
are being made towards less defect generation during exposure and more defect removal through pre-soak and postsoak
We have experienced a variety of immersion defects and classified them into four types: bubble defect, water mark
defect (T-top & Stain), swelling defect and bridge defect (Macro & Micro). We have worked very hard to reduce each
immersion defects with immersion exposure and system. In this paper, we investigate method to reduce each
immersion defects: bubble, water mark, swelling and bridge through our experiment.
In this paper, we will present experimental results on 45nm node patterning of DRAM and some technical issues for
polarized illumination in hyper NA imaging. First, practical k1 limit of 1.2NA ArF immersion system is investigated
through experiment. Process window and mask error enhancement factors are measured with respect to various design
rules, i.e., different k1 levels at fixed NA. Reasonable process window and MEEF value of around 3 are achieved in
DRAM gate and isolation layers at around 0.28 k1 regime. It is obvious that feasibility of this lowered k1 was realized
by the help of polarized illumination when we compared the results with that of 60nm patterning at 0.93NA tool -
corresponding k1 is 0.29 - without polarized illumination. Then consideration about degree of polarization state must
come next to the benefit of polarized illumination. Input polarization state is changed by birefringence of lens or mask
materials but it is very difficult to correlate the birefringence level and critical dimension of patterns experimentally.
Double exposing method was contrived to measure the effect of degree of polarization on DICD. And we also measure
the polarization dependent transmittance of light on mask by using 1.2NA immersion scanner. As a result, birefringence
and mask feature interaction with light seems not to be a serious issue for 45nm hyper NA polarized imaging.
As the pattern size decreases, the thickness of resist also should be decreased owing to the pattern collapse problem. So the using of surfactant containing rinse material, instead of DI water, can be a solution to the collapse problem. The developing of Bottom Anti Reflective Coating (BARC) that has high etch rate will be helpful to the collapse issue because it enables low thickness resist process and pattern collapse will be decrease. In this paper, Polyacetal, polyacrylate and polyesters BARCs were evaluated. Polyacetal type BARC shows best coating property. Regardless of the topology, polyacetal type BARC shows good conformality. However, polyacrylate and polyesters show coating fail on the topology wafer. In terms of pattern collapse, polyacetal type BARC also shows best results. Among the three types of BARC, ArF BARC that is made by polyester resin shows highest etch rate after 2000ÅBRAC etch. However, when the etching target is 60nm, all BARCs have same etch rate. For the matching with line and space resist, all these three BARCs show good profile. However, polyester type BARC does not match with contact hole resist and could not define contact hole pattern.