Recent advances in the integrated electronic circuit industry have spurred efforts to develop technologies that efficiently integrate optics and electronics on a single Complementary Metal Oxide Semiconductor (CMOS) chip. Such CMOS technologies can significantly increase circuit functionality and performance at low fabrication and system cost, thereby accelerating the trend of significant growth in this area. The new functionality could include optical based sensors, image processing, and intelligent optical read heads for faster and more efficient data sorting and searching. The reliability of such monolithic CMOS based functions would be drastically improved relative to their bulk optic counterparts. In the optical telecommunications industry, short haul fiber links would benefit from low cost, silicon CMOS based photoreceivers. One of the primary challenges facing the designers in implementing CMOS based optoelectronic circuits is opto-electrical conversion efficiency. The poor optical responsivity of silicon leads to a bottleneck in the optical to electrical conversion for CMOS based photodetectors. This can be compensated in part through more efficient receiver electronics. Efforts have been made to provide mixed signal circuit design to analyze CMOS based high performance, low noise, integrated receiver circuits. This paper evaluates the performance analysis of five types of photoreceiver configurations that were designed for specific applications.
KEYWORDS: Data processing, Data storage, Logic, Data communications, Computer architecture, Optical communications, Photonic devices, Very large scale integration, Photodetectors, Spatial light modulators
The ever-increasing demand for communication bandwidth and system interconnectivity has been a motivating factor behind the integration of optoelectronics devices and conventional data processing circuitry. Based on the smart-pixel architectures first developed in the last decade, the architecture presented here monolithically integrates optical sensors with silicon CMOS-based circuitry to produce a generically programmable smart-pixel array. Two generations of the architecture are described and compared. We have proposed a reconfigurable photonic information-processing chip based on photonic VLSI device technology. Integrating detectors into a SIMD array removes the bottleneck associated with fetching slices of data. By fabricating the detectors along with logic circuits in a bulk CMOS process, the cost is minimized. The modular nature of the array organization facilitates replication of the configurable architecture for smart-pixel research (CASPR) concept into large arrays without a significant increase in design overhead. Thus, the CASPR architecture can provide the maximum flexibility associated with a reconfigurable smart-pixel array. Finally, we implement two design iterations of the CASPR architecture and show how the architecture might be used in a page-oriented optical data processing application.
The ever increasing demand for communication bandwidth and system interconnectivity has been a motivating factor behind the integration of optoelectronics device and conventional data processing circuitry. Over the last two decades, fiber optic components have become the dominant technology in the telecommunications industry. In last 5 years, optical interconnection techniques have been suggested as a solution to the interconnect density and bandwidth problems faced by electrical systems at the cabinet, PC-board and even chip level. Based on the smart pixel architectures in the last decade, the proposed chip monolithically integrates optical sensors with silicon CMOS based circuitry. This project incorporates an instruction fetch unit (IFU), that fetches the instructions from an external host computer, and a 2D-array of one-bit smart pixels called the processing element (PE). Each PE consists of an ALU, control logic, dual port register memory bank, photo-receiver circuit and associated driver circuits. By tiling these smart pixels in 2D, it is possible to form a programmable smart pixel array that is well suited to read optical page-oriented data types. The CASPR chip contains a 4x4 array of PEs connected to a single IFU. Inter PE communication has been established through nearest neighbor communication. Simultaneous communication to all the PEs is possible through global communication. The instruction set for this architecture is 17-bit long. The chip has been successfully fabricated in 0.5μ technology. We present in this paper the design and initial test results from the recent fabrication.