High data transfer rate has been demanded for data storage devices along increasing the storage capacity. In order to
increase the transfer rate, high-speed data processing techniques in read-channel devices are required. Generally, parallel
architecture is utilized for the high-speed digital processing. We have developed a new architecture of Interpolated
Timing Recovery (ITR) to achieve high-speed data transfer rate and wide capture-range in read-channel devices for the
information storage channels. It facilitates the parallel implementation on large-scale-integration (LSI) devices.