Fabrication of defect free EUV masks including their inspection is the most critical challenge for implementing EUV
lithography into semiconductor high volume manufacturing (HVM) beyond 22nm half-pitch (HP) node. The contact to
bit-line (CB) layers of NAND flash devices are the most likely the first lithography layers that EUV will be employed for
manufacturing due to the aggressive scaling and the difficulty for making the pattern with the current ArF lithography.
To assure the defect free EUV mask, we have evaluated electron beam inspection (EBI) system eXplore™ 5200
developed by Hermes Microvision, Inc. (HMI) . As one knows, the main issue of EBI system is the low throughput.
To solve this challenge, a function called Lightning Scan™ mode has been recently developed and installed in the system,
which allows the system to only inspect the pattern areas while ignoring blanket areas, thus dramatically reduced the
overhead time and enable us to inspect CB layers of NAND Flash device with much higher throughput.
In this present work, we compared the Lightning scan mode with Normal scan mode on sensitivity and throughput. We
found out the Lightning scan mode can improve throughput by a factor of 10 without any sacrifices of sensitivity.
Furthermore, using the Lightning scan mode, we demonstrated the possibility to fabricate the defect free EUV masks
with moderate inspection time.
Achieving the specifications of resolution, sensitivity and line width roughness (LWR) of wafer resist is one of the top
challenges of bringing extreme ultraviolet lithography (EUVL) into high volume manufacturing. Contributions to the
resist LWR on wafer can be divided into two categories; chemical properties of the resist and aerial image. Chemical
properties of the resist are complicated and many factors contribute to LWR, such as polymer size, sensitivity, surface
reaction etc. Aerial image LWR is much simply determined by the optical properties of a mask and a scanner. Since
very small LWR value of the resist is needed, EUV mask LWR is also set very severely from ITRS <sup></sup>.
In our previous work <sup></sup>, we demonstrated current mask LWR as comparing them with mask resist LWR and absorber
LWR. As a result, we found that the absorber's LWR almost depends on resist patterning.
In this paper, we will present the influence of resist patterning on absorber LWR comparing resist materials and EB
tools. From the results, LWR has been reduced by 10-20% by improving EB tool. However, the LWR value at line and
space pattern for 22nm-hp case have not met target of ITRS' roadmap while, by using Non-CAR, the LWR value has
met the target. In particularly, the value at isolated line is dramatically improved using Non-CAR.
OPC (Optical Proximity Correction) technique is getting more complicated towards 32 nm technology node and beyond,
i.e. from moderate OPC to aggressive OPC. Also, various types of phase shift mask have been introduced, and their
manufacturing process is complicated. In order to shorten TAT (Turn around time), mask design technique needs be
considered in addition to lithography technique.
Furthermore, the lens aberration of the exposure system is getting smaller, so its current performance is very close to the
ideal. On the other hand, when down sizing of device feature size reaches the 32nm technology node, cases begin to be
reported where the feature dimension is not matched between a mask pattern and the corresponding printed pattern.
Therefore, it is indispensable to understand the pattern size correlation between a mask and the corresponding printed
wafer in order to improve the processing accuracy and the quality in the situation where the device size is so small that
the low k1 lithography is widely used in production.
One of the approaches to improve the estimated accuracy of lithography is the use of contour data extracted from mask
SEM image in addition to the application of a mask model.
This paper describes a newly developed integration system that aims to solve the issues above, and its applications. This
is a system that integrates mask CD-SEM (Critical Dimension-Scanning Electron Microscope) CG4500, wafer CD-SEM
CG4000, OPC evaluation system DesignGauge, all manufactured by Hitachi High-Technologies.
The measurement accuracy improvement was examined by executing a mask-wafer same point measurement, i.e.
measurement of the corresponding points, with same measurement algorithm utilizing the new system. First, we
measured mask patterns and verified the validity based on the measurement value, the image, the measurement
parameter and the coordinates. Then a job file was formulated for a wafer CD-SEM using the new system so as to
measure the corresponding patterns that were exposed using the mask. In addition, the average CD measurement was
tried in order to improve the capability.
Furthermore, in order to estimate the pattern shape with high accuracy, a contour was calculated from a mask SEM
image, and the result was used with the design data in a litho simulation. This realizes a verification that includes mask
This system is expected to be beneficial for both mask makers and device makers.
As the pattern feature sizes become smaller, photomask assurance by one-dimensional criteria using a CD-SEM is reaching its limits. For instance, minute steps generated by OPC (Optical Proximity Correction), especially under the influence of corner rounding, are hard to measure. Thus, photomask assurance by means of two-dimensional features has been studied.
Conventionally, in simulations to predict the printed shape on the wafer, OPCed data pattern have been used. While the OPCed data pattern represents the ideal pattern fidelity, actual pattern on a real photomask is different from the ideal shape. In addition, the increase of MEEF (Mask Error Enhancement Factor), along with the fine-than-ever pattern feature size, emphasizes the difference between the simulation result and the actually printed result on the wafer. To realize the two-dimensional assurance, we have to think of a method to predict the wafer image accurately. This is also important when we have to verify and manage the lithographic hotspots.
For this purpose, we have been studying a mask model, a technique to take into consideration the actual pattern fidelity on the photomask, by modeling mask patterns' linearity, proximity, corner-rounding, etc., for each mask making process. By applying the mask model to OPCed design pattern, mask pattern shapes were found to be accurately predicted before mask making.
Furthermore, we studied hotspot verification flow using the mask model. By the application of the mask model on the data pattern for the optical simulation, we accurately predicted the shape printed on the wafer, and accurately verify hotspots. This is expected to lead to assurance of photomask using two-dimensional shape.
In the continuous battle to improve critical dimension (CD) uniformity, especially for 45-nanometer (nm) logic
advanced products, one important recent advance is the ability to accurately predict the mask CD uniformity
contribution to the overall global wafer CD error budget. In most wafer process simulation models, mask error
contribution is embedded in the optical and/or resist models. We have separated the mask effects, however, by
creating a short-range mask process model (MPM) for each unique mask process and a long-range CD
uniformity mask bias map (MBM) for each individual mask. By establishing a mask bias map, we are able to
incorporate the mask CD uniformity signature into our modelling simulations and measure the effects on global
wafer CD uniformity and hotspots. We also have examined several ways of proving the efficiency of this
approach, including the analysis of OPC hot spot signatures with and without the mask bias map (see Figure 1)
and by comparing the precision of the model contour prediction to wafer SEM images. In this paper we will
show the different steps of mask bias map generation and use for advanced 45nm logic node layers, along with
the current results of this new dynamic application to improve hot spot verification through Brion Technologies'
model-based mask verification loop.
One of the most critical points for accurate OPC is to have accurate models that properly simulate the full process from
the mask fractured data to the etched remaining structures on the wafer. In advanced technology nodes, the CD error
budget becomes so tight that it is becoming critical to improve modeling accuracy. Current technology models used for
OPC generation and verification are mostly composed of an optical model, a resist model and sometimes an etch model.
The mask contribution is nominally accounted for in the optical and resist portions of these models. Mask processing
has become ever more complex throughout the years so properly modeling this portion of the process has the potential
to improve the overall modeling accuracy. Also, measuring and tracking individual mask parameters such as CD bias
can potentially improve wafer yields by detecting hotspots caused by individual mask characteristics. In this paper, we
will show results of a new approach that incorporates mask process modeling. We will also show results of testing a
new dynamic mask bias application used during OPC verification.