The Self-Aligned Quadruple Patterning (SAQP) process is one of the most suitable techniques for the patterning of under-20 nm half-pitch lines and spaces (L/S) patterns because it requires only one lithography step, resulting in a relatively low process cost. A serious problem when applying the SAQP process to real devices is the printability of defects in the photomask to the wafer because the effect of the mask defects may be enlarged when the defects are transferred to the spacer pattern. In this study, we evaluate the mask defect printability for both opaque and clear defects in the SAQP process in order to clarify the limit size of the defects on the photomask and to clarify whether the acceptable mask defect size given by ITRS was too small. The defect sizes of both the opaque and clear defects were relaxed as the wafer process progressed from lithography to SAQP. The acceptable mask defect size in the SAQP process found to be 70 nm, which is relaxed from that in ITRS2013.
We have constructed a hotspot management flow and applied the flow to large-scale integration (LSI) manufacturing in the ultralow k1 lithography era. This flow involves three main management steps: hotspot reduction, hotspot extraction, and hotspot monitoring. Hotspot reduction works with lithography-friendly restricted design rule (RDR) and manufacturability check (MC). Hotspot extraction is carried out with a view to realizing short operation time and accurate extraction. Hotspot monitoring is achieved with tolerance-based verification in the mask fabrication process and wafer process (lithography and etching). These technology elements could be integrated into the LSI fabrication flow for reduction of total cost, quick turnaround time (TAT), and ramp-up to volume production. In addition to discussion of the technology elements in hotspot management, we also provide typical applications for important decisions in LSI fabrication: photomask availability for any exposure tools ("exposure tool yokoten") and process condition updates in LSI fabrication.
We constructed hot spot management flow with a die-to-database inspection system that is required for both hot
spot extraction accuracy and short development turn-around-time (TAT) in low k1 lithography. The die-to-database
inspection system, NGR-2100, has remarkable features for the full chip inspection within reasonable operating time.
The system provided higher hot spot extraction accuracy than the conventional optical inspection tool. Also, hot spots
extracted by the system could cover all killer hot spots extracted by electrical and physical analysis. In addition, the new
hot spot extraction methodology employing the die-to-database inspection system is highly advantageous in that it
shortens development TAT by two to four months. In the application to 65nm node CMOS, we verified yield
improvement with the new hot spot management flow. Also, the die-to-database inspection system demonstrated
excellent interlayer hot spot extraction from the viewpoint of LSI fabrication.
Small process window in ultra-low k1 lithography (k1<0.35) poses difficulties for judgment of the availability of high-end photomasks for preliminary exposure tools for high volume production ramp-up. Also, our previous judgment flow of high-end photomasks availability has several concerns. Therefore, the ultra-low k1 lithography requires accurate judgment methodologies for high-end photomask availability with short turn-around-time (TAT). In this paper, we propose a new concept concerning hot spot-based judgment flow which consists of two stages for high-end photomask availability. Our proposed flow permits judgment of high-end photomask availability for high volume production ramp-up with short TAT.
We have constructed a hot spot management flow for LSI manufacturing in the ultra-low k1 lithography era. This flow involves three main management steps: hot spot reduction, hot spot extraction and hot spot monitoring. Hot spot reduction works for lithography friendly restriction (RDR) and manufacturability check (MC). Hot spot extraction is carried out with consideration of short turn-around-time (TAT), accurate extraction and convenient functions such as hot spot for interlayers. Hot spot monitoring is achieved with tolerance-based verification in mask fabrication process and wafer process (lithography and etching). These technology elements were integrated into the actual LSI fabrication flow. The application of this concept to LSI manufacturing could contribute to reduction of total cost, quick TAT and ramp up to volume production.
A novel, accurate, one-dimensional process proximity correction method is proposed. The method is based on the relationship between a line width variation and the bias which should be corrected. This relationship is characterized by the Total process proximity-based Correction Factor (TCF) which is defined as the slope of the wafer CD variation curve to the mask design CD under a constant pattern pitch condition. At a TCF greater than 1, patterns should be corrected with values less than the line width deviation. By applying the new PPC method to 0.25 micrometer logic gate patterns, a correction rule table was experimentally obtained. The new PPC mask fabricated with the correction rule exhibited a significant improvement over the conventional correction technique in the logic device.