Mr. Saumil Shah Profile

Saumil Shah

at Blaze DFM Inc

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Author

Publications (2)

Proceedings Article | 1 April 2008 Paper

Shaping gate channels for improved devices

Puneet Gupta, Andrew Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester

Proceedings Volume 6925, 69250I (2008) https://doi.org/10.1117/12.772889

KEYWORDS: Transistors, Ions, Capacitance, TCAD, Mathematical modeling, Manufacturing, Optimization (mathematics), Standards development, Diffusion, Oxides

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Proceedings Article | 14 March 2006 Paper

Lithography simulation-based full-chip design analyses

Puneet Gupta, Andrew Kahng, Sam Nakagawa, Saumil Shah, Puneet Sharma

Proceedings Volume 6156, 61560T (2006) https://doi.org/10.1117/12.658129

KEYWORDS: Lithography, Capacitance, Resolution enhancement technologies, Device simulation, Error analysis, Optical proximity correction, Databases, Resistance, Shape analysis, Critical dimension metrology

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Today's design flows sign-off performance and power prior to application of resolution enhancement techniques (RETs). Together with process variations, RETs can lead to substantial difference between post-layout and on-silicon performance and power. Lithography simulation enables estimation of on-silicon feature sizes at different process conditions. However, current lithography simulation tools are completely shape-based and not connected to the design in any way. This prevents designers from estimating on-silicon performance and power and consequently most chips are designed for pessimistic worst-cases. In this paper we present a novel methodology that uses the result of lithography simulation for estimation of performance and power of a design using standard device- and chip-level analysis tools. The key challenge addressed by our methodology is to transform shapes generated by lithography simulation to a form that is acceptable by standard analysis tools such that electrical properties are preserved. Our approach is sufficiently fast to be run full-chip on all layers of a large design. We observe that while the difference in power and performance estimates at post-layout and on-silicon is small at ideal process conditions, it increases substantially at non-ideal process conditions. With our RET recipes, linewidths tend to decrease with defocus for most patterns. According to the proposed analyses of layouts litho-simulated at 100nm defocus, leakage increases by up to 68%, setup time improves by up to 14%, and dynamic power reduces by up to 2%. The key challenge addressed by our methodology is to transform shapes generated by lithography simulation to a form that is acceptable by standard analysis tools such that electrical properties are preserved. Our approach is sufficiently fast to be run full-chip on all layers of a large design. We observe that while the difference in power and performance estimates at post-layout and on-silicon is small at ideal process conditions, it increases substantially at non-ideal process conditions. With our RET recipes, linewidths tend to decrease with defocus for most patterns. According to the proposed analyses of layouts litho-simulated at 100nm defocus, leakage increases by up to 68%, setup time improves by up to 14%, and dynamic power reduces by up to 2%.

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