As future patterning processes reach the limit of lithographic printability, continuous innovation in mandrel trim or shrink strategies are required to reach sub-20 nm line-space patterning. Growing concerns of lithography defectivity, mask selectivity, line edge roughness (LER), line width roughness (LWR), and critical dimension uniformity (CDU) present significant challenges towards this goal. The authors compare various alternative mandrel trim strategies to highlight potential solutions and drawbacks towards enabling successful printing of mandrels used in extreme ultraviolet (EUV) multi-patterning schemes. Through this comparison, the authors demonstrate the challenges of maintaining adequate pattern transferability while keeping aspect ratio-driven line roughness and material selectivity under control. By process partitioning, the limitations of traditional lithography and etch trimming strategies are highlighted, suggesting the need for new methods of CD reduction after the pattern has been transferred. These new trimming methods offer flexibility in CD control without negatively impacting the mandrel profile and demonstrates better tunability across different material sets, allowing for evaluation of different mask and mandrel material combinations for downstream process optimization.
Emerging memory devices, such as MRAM, RRAM, and PCM, plays an important role in in-memory computation technology which can lead to significant acceleration for machine learning and AI applications.[1-3] The basic structure of these memory cell is simply a pillar made of a wide range of materials, however, the local CD uniformity (LCDU) of the pillars is especially crucial for these memory devices. The stringent LCDU requirement derives from either the intrinsic small resistance difference between the two memory states or the requirement for creating a large number of memory states within a small range of resistance. Apparently, the stochastic variation in physical dimension will correspond to the variation in resistance from cell to cell, which will affect the correct readout of the memory states and fail the device.
Because the “local” CDU in this context refers to the variation within the memory array, i.e. typically within several um, it is almost impossible to correct by utilizing existing advanced tools or process control techniques. In this work, we will demonstrate four promising options to address the stochastic effect in LCDU of pillars: a) adopting new resists, b) PTD and NTD shrink, c) DSA, d) cross-SADP. Fig. 1 shows the general approach to achieve better LCDU by printing larger CD at litho and shrink by post-litho processing. Here we carefully characterize two shrinking techniques and its efficacy on LCDU improvement. Fig. 2 shows two alternative approaches, i.e. DSA and cross-SADP. We will carefully explore these four approaches for LCDU improvement with thorough characterization and analysis. Subsequent pattern transfer and the retention of the LCDU improvement and cost/quality trade-off will also be discussed. Defectivity learning will also be discussed.