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With growing process complexity and the increasing number of process steps, early prediction of device performance has become an important task in semiconductor manufacturing process control. Machine learning (ML) techniques allow us to link in-line measurements to End-Of-Line (EOL) electrical tests. In our paper, we use reflectance spectra obtained from the scatterometry tool to predict both metal-line resistance and capacitance. We used IMEC N14 process flow with LELE double patterning at the M1 stage. Special designs-of-experiments (DOE) for multiple parameters allowed us to create a metrology solution for the entire process window and test its accuracy for all POI. Induced variations of both line CDs and space CDs, together with specially designed measurement sites, created wide variations both in metal-line resistance and capacitance. Reflectance spectra were collected in-line at two process steps defining metal lines: HM etch and Cu CMP at multiple targets, including E-test measurement sites, together with reference metrology for overlay (OV) and CD (by using Diffraction-Based-Overlay (DBO) and CD SEM). EOL electrical test results were used for the ML training procedure for early prediction of patterning effects (both CD and OL) on electrical performance enabling early decisions and cost reduction by discarding out-of-spec wafers before they reached the electrical test. It was shown that ML OCD predictive techniques are complimentary to the OCD model-based solutions for geometrical parameters widely used for in-line APC.
Up until now, the main driving force for the semiconductor industry is the continual shrinkage of device feature sizes, thereby incorporating more devices per unit area, reducing manufacturing cost and enhancing their performance have been achieved. However, the shrinkage of feature size leads to a reduction of process window imposing an extremely tight requirement for parameters such as critical dimension (CD), edge and width roughness of spaces/trenches, contacts, lines, and tip to tip (T2T) values. At sub 14 nm technology nodes these parameters have a significant influence on the overall device performance. With EUV based pattering becoming the sole option at these advanced nodes, a thorough characterization of the patterning process is of utmost importance before it can be a high-volume manufacturing solution.<p> </p> In this work, we show how e-beam inspection has been used to characterize a single exposure EUV M2 (Metal 2 layer, BEoL) to have an understanding of the different hotspots and intra-field signatures present. Design Based Metrology (DBM) with wide SEM image was employed to measure CD distribution and Edge Placement Error (EPE) distribution of metal layer pattern on the 10nm logic wafer.