EUV lithography is being prepared for insertion into the semiconductor production processes to continue the reduction of critical feature sizes at subsequent process nodes. To support that EUV wafer lithography development and production, the EUV photomask infrastructure similarly needs to be ready to support the shipment of EUV photomasks. EUV photomasks will require tighter process controls and tighter defect specifications to meet the requirements necessary for the wafer manufacturing insertion node. The novelty of the EUV lithography process combined with the high degree of complexity of the EUV photomask structure and process each contribute to the tightening of EUV photomask requirements, requiring accurate metrology to ensure fidelity to the photomask specifications. To fully address the industry requirements for EUV defectivity review and actinic mask qualification, ZEISS and the SUNY POLY SEMATECH EUVL Mask Infrastructure consortium have developed and commercialized the EUV aerial image metrology system, the AIMSTM EUV. The first commercial platform is already installed at a customer site and is available to support the EUV photomask production pipeline. This paper shows how the proven technology of the ZEISS aerial image system implemented into the AIMSTM EUV platform supports EUV photomask production in the back end of the line of Intel photomask manufacturing shop. Alongside with describing the essential development phases of the platform at customer site, examples of the reproducible measurement quality, as well as stability of the imaging fidelity of the system in production will be shown. In addition, the system output together with the experience on uptime and availability of the AIMSTM EUV platform in production is presented.
Pixelated phase masks rendered from computational lithography techniques demand one generation-ahead mask
technology development. In this paper, we reveal the accomplishment of fabricating Cr-less, full field, defect-free
pixilated phase masks, including integration of tapeout, front-end patterning and backend defect inspection, repair,
disposition and clean. This work was part of a comprehensive program within Intel which demonstrated microprocessor
To pattern mask pixels with lateral sizes <100nm and vertical depth of 170nm, tapeout data management, ebeam write
time management, aggressive pattern resolution scaling, etch improvement, new tool insertion and process integration
were co-optimized to ensure good linearity of lateral, vertical dimensions and sidewall angle of glass pixels of arbitrary
pixelated layout, including singlets, doublets, triplets, touch-corners and larger scale features of structural tones
including pit/trench and pillar/mesa. The final residual systematic mask patterning imperfections were corrected and
integrated upstream in the optical model and design layout.
The volume of 100nm phase pixels on a full field reticle is on the order tera-scale magnitude. Multiple breakthroughs in
backend mask technology were required to achieve a defect free full field mask. Specifically, integration of aerial
image-based defect inspection, 3D optical model-based high resolution ebeam repair and disposition were introduced.
Significant reduction of pixel mask specific defect modes, such as electro static discharge and glass pattern collapse,
were executed to drive defect level down to single digit before attempt of repair. The defect printability and repair yield
were verified downstream through silicon wafer print test to validate defect free mask performance.
The reticle manufacturing process induces various defects on the mask that need to be repaired. Missing absorber or clear defects are often repaired by depositing a carbon-based material (depo) using a Focused Ion Beam (FIB) tool. Few cases of such depo repairs on defects in between nested contacts on attenuated phase shift masks were found to fail upon use in high volume wafer manufacturing factories. With the goal of first reproducing the problem in the mask shop, a controlled set of depo repairs were performed on a test reticle and sequentially exposed on a DUV flood exposure system, emulating stepper exposure. The repair AIMSTM printability and AFM height profiles were measured before and after each exposure step. With incremental exposures, AIMSTM results showed the repaired contacts gradually printing larger in size and AFM results showed the tail of the depo repair (also referred to as depo overspray or halo) correspondingly receding with exposure. This suggests that the tail of the depo presumably contributes to the correct print CD of the repaired contact, and its gradual recession with exposure was likely causing the contacts to print larger, ultimately even bridging with the neighboring nested contact in some cases. This mechanism was confirmed by checking similar repairs on several production masks already being used in the wafer factories, at different stages of exposure. Subsequently, a novel post-repair process was developed which achieves rapid overspray removal thereby avoiding any further change in these repairs and associated wafer yield impact upon prolonged use on scanners.
Silicon (Si) capping for extreme ultra-violet lithography (EUVL) multilayer (ML) mask blank presents certain disadvantages, such as prone to oxidation, low chemical resistance, low SiO2 buffer layer etch selectivity to the capping layer. These performance and process issues with Si capped ML mask blank will reduce mask lifetime and require tighter process margin during EUVL mask processing. Using ruthenium (Ru) to replace Si for ML capping has been investigated previously for EUVL optics application. High oxidation resistance for Ru capped ML optics has been demonstrated. In this study, we have further demonstrated that Ru capped ML mask blank can also overcome the process issues that are associated with the Si capping. Our mask patterning results showed very high absorber and buffer etch selectivity to the Ru capping layer. As a result, uniform mask reflectivity after mask patterning is obtained.
In this paper we will present detailed Ru capped ML mask fabrication results, such as etch profile, etch selectivity to the ML capping, as well as mask quality characterization results, which include ML performance data comparison before and after the mask patterning.
As requirement of CD uniformity on photomask continue to tighten with advanced logic and memory devices, new process technologies will be needed to be developed to address the gap of process capability. For instance, a less than 20 nm CD range will be required on a 0.18 micrometer generation logic devices with a nominal field area of 120 X 120 mm. New technologies such as high energy e-beam write (to reduce forward scattering), advanced e-beam photoresist and plasma etch processes are currently being developed to achieve such stringent CD uniformity specifications. One of the key issues of plasma etch technology is related to microloading effects which accounts for a major portion of CD budgets. In this work, an engineering test mask was designed to identify etch microloading mechanisms and to improve performance of a standard Magnetic-Enhanced Reactive Ion Etch (MERIE) process. Additional comparison of CD microloading was also made with an Inductively-Coupled Plasma (ICP) etch process.
Fabrication of 0.18 micrometers generation clearfield logic device photomask with plasma etch was compared with wet etch method in current 0.25 micrometers mask technology. Spatial consistency between the resist develop and plasma etch modules was critical to achieve < 25 nm CD rng manufacturable process. CD linearity for 0.6 to 3.0 micrometers lines and isolated-nested CD bias for 1.0 micrometers lines were both improved with the plasma etch process. Resist loading and proximity effect is critical for plasma etched clearfield mask and can account for up to 20 nm range of overall CD budget.