In the process of optical proximity correction, layout edge or fragment is migrating to proper position in order
to minimize edge placement error (EPE). During this fragment migration, several factors other than EPE can be also
taken into account as a part of cost function for optimal fragment displacement. Several factors are devised in favor of
OPC stability, which can accommodate room for high mask error enhancement factor (MEEF), lack of process window,
catastrophic pattern failure such as pinch/bridge and improper fragmentation. As technology node becomes finer, there
happens conflict between OPC accuracy and stability. Especially for metal layers, OPC has focused on the stability by
loss of accurate OPC results. On this purpose, several techniques have been introduced, which are target smoothing,
process window aware OPC, model-based retargeting and adaptive OPC. By utilizing those techniques, OPC enables
more stabilized patterning, instead of realizing design target exactly on wafer.
Inevitably, post-OPC layouts become more complicated because those techniques invoke additional edge, or
fragments prior to correction or during OPC iteration. As a result, jogs of post OPC layer can be dramatically increased,
which results in huge number of shot count after data fracturing. In other words, there is trade-off relationship between
data complexity and various methods for OPC stability.
In this paper, those relationships have been investigated with respect to several technology nodes. The mask
shot count reduction is achieved by reducing the number of jogs with which EPE difference are within pre-specified
value. The effect of jog smoothing on OPC output - in view of OPC performance and mask data preparation - was
studied quantitatively for respective technology nodes.
Various resolution enhancement techniques have been proposed in order to enable optical lithography
at low k1 imaging, e.g. alt-PSM (phase shift mask), chromeless phase lithography (CPL), double
exposure technique (DET) and double dipole lithography (DDL). In spite of its low throughput in
production, DDL technique is a very attractive solution for low k1 process because of the relatively low
cost of binary or attenuated phase shift masks, which can be combined with strong dipole illuminations
and flexible SRAF rule to enhance the process window. Another attraction of DDL is that dry scanner
still can be used for 45nm node instead of expensive immersion lithography process.
In this paper, two aspects for DDL application have been focused on. The first one is OPC optimization
method for DDL, which includes SRAF optimization, mask decomposition and pixel-based OPC. The
whole flow is optimized specifically for DDL to achieve satisfactory pattern results on wafer. The
second is the overlay issue. Since two DDL masks are exposed in turn, the overlay variation between
two masks becomes dominant factor deteriorating pattern quality. The effect of overlay tolerance is also
studied through process window simulation.
DDL has been demonstrated to be capable of 45nm node logic with dry scanner. The pattern fidelity and
process window of 45nm node SRAM & Random Logic are evaluated for active/gate layer and dark
field metal layer.
Proc. SPIE. 6283, Photomask and Next-Generation Lithography Mask Technology XIII
KEYWORDS: Lithography, Electron beam lithography, Data modeling, Deep ultraviolet, Scanners, Photomasks, Critical dimension metrology, Semiconducting wafers, Laser systems engineering, Back end of line
The higher productivity of the DUV laser mask lithography system compared to the 50-KeV e-beam system offers the benefit of mask cost down at low k1 lithographic process. But the major disadvantage of the laser mask writing system is rounding effect of contact hole and line end. In this paper, we study wafer process margin effect of corner rounded contact hole and present mask CD specification of corner rounded contact hole written by DUV laser lithography system compared to 50KeV writing tool. The contact hole rounding changes contact hole area at the same mask CD and also change MEEF(Mask Error Enhancement Factor) even though the contact hole area is compensated by adjusting mask bias. If one change EBM3500 mask writer machine to Alta4300 mask writer machine for 160nm contact hole using KrF and 6% HT-PSM, one has to change mask bias, 3.2nm, to meet same wafer process condition.. The MEEF of ALTA4300 mask is 1.6% higher than that of EBM3500 mask at same effective target mask CD. And the mask CD specification written by ALTA4300 has to be set more tightly about 1.3 ~ 1.5% to meet same wafer process margin with EBM3500 mask.
The advanced lithography needs to be tightly controlled in various areas of lithography. The mask CD specification is one of new areas required much tighter control. Typically, mask CD error can be sorted as two different categories. One is Mean-to-target (MTT) and another is CD uniformity (CDU). The MTT is the difference between the target value and the average value of the measured CD on the mask. CDU means CD uniformity across mask. Those two potential errors can be magnified on the wafer level due to the MEEF. To overcome the MTT, we can adjust expose dose to compensate mask CD error so that we achieve targeted CD on the wafer level. However, the changing expose dose also induces process window change due to the MEEF. It means that we have narrower process window even if we get the targeted CD on the wafer level. On the other hand, CDU can give two different effects on the wafer level. One is narrower process window due to magnified ACLV (Across Chip Line-width Variation) due to the MEEF. Another effect of CDU is the poor OPC accuracy caused by different MEEF as function of pitch. For example, we assume that CD difference of dense line and isolated line is 10 nm on the mask. However, on the wafer, this 10 nm can be magnified as 20 nm by MEEF difference between two structures. Therefore, we think that the mask specification needs to take account those effects. In this paper, we will show technical data to prove how MTT and CDU impact on process window and OPC accuracy. And we will show how we have to make mask specification to overcome those effects.
Since an OPC engine makes model to fit wafer printed CD of OPC test mask to simulation CD of test pattern layout, the target CD of OPCed mask is not design CD but the CD of OPC test mask. So, the CD difference between OPC test mask and OPCed mask is one of the most important error source of OPC. We experimentally obtained OPC CD error of several patterns such as iso line, iso space, dense line, line end, effected by the mask MTT (mean to target) difference of the two masks on of 90nm logic pattern with an ArF attenuated mask having designed different MTT. The error is compared to simulated data that is calculated with MEEF (mask error enhancement factor) and EL (exposure latitude) data of these patterns. The good agreement of the experimental and calculated OPC error effected mask MTT error can make OPC error are predicted by mask CD error. Using by these calculation, we made mask CD window to meet OPC spec for 90nm ArF process.
Overlay mismatch of pre/post etch on metal layer is caused by asymmetric metal deposition on overlay mark. The major components of the mismatch are known to be composed of wafer scale and rotation caused by self-shadowing effect and CMP process, respectively. The behavior of each component was observed according to the changes in overlay mark shapes, metal thickness and CMP process conditions in this study. The overlay difference according to metal overhang on overlay mark was also investigated. It was found that overlay mismatch was reduced when the metal overhang on overlay mark happens, and over-polishing overlay mark during W CMP prevents formation of the metal overhang and increases wafer scale mismatch.