Dr. Sébastien Soulan Profile

Dr. Sébastien Soulan

at CEA-LETI

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Publications (8)

Proceedings Article | 22 February 2021 Poster + Presentation + Paper

Detection and correlation of yield loss induced by color resist deposition deviation with a deep learning approach applied to optical acquisitions

Thomas Alcaire, Delphine Le Cunff, Jean-Hervé Tortai, Sebastien Soulan, Victor Gredy, Maxime Templier, Mehdi Kessar, Raffaele Bianchini, Audrey Berthoud

Proceedings Volume 11611, 116112G (2021) https://doi.org/10.1117/12.2582058

KEYWORDS: RGB color model, Semiconducting wafers, Statistical modeling, Metrology, Interferometry, Wafer-level optics, Reflectometry, Process control, Optical filters, Model-based design

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Proceedings Article | 13 May 2013 Paper

S-Genius, a universal software platform with versatile inverse problem resolution for scatterometry

David Fuard, Nicolas Troscompt, Ismael El Kalyoubi, Sébastien Soulan, Maxime Besacier

Proceedings Volume 8789, 878919 (2013) https://doi.org/10.1117/12.2020674

KEYWORDS: Scatterometry, Optimization (mathematics), Inverse problems, Refractive index, Neural networks, Metrology, Lithography, Diffraction, Process control, Data modeling

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Proceedings Article | 21 March 2012 Paper

Sub-20nm hybrid lithography using optical, pitch-division, and e-beam

J. Belledent, M. Smayling, J. Pradelles, P. Pimenta-Barros, S. Barnola, L. Mage, B. Icard, C. Lapeyre, S. Soulan, L. Pain

Proceedings Volume 8323, 83230F (2012) https://doi.org/10.1117/12.916486

KEYWORDS: Electron beam lithography, Photomasks, Lithography, Optical lithography, Logic, Optics manufacturing, Semiconducting wafers, Double patterning technology, Neodymium, Scanning electron microscopy

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A roadmap extending far beyond the current 22nm CMOS node has been presented several times. [1] This roadmap includes the use of a highly regular layout style which can be decomposed into "lines and cuts."[2] The "lines" can be done with existing optical immersion lithography and pitch division with self-aligned spacers.[3] The "cuts" can be done with either multiple exposures using immersion lithography, or a hybrid solution using either EUV or direct-write ebeam.[ 4] The choice for "cuts" will be driven by the availability of cost-effective, manufacturing-ready equipment and infrastructure. Optical lithography improvements have enabled scaling far beyond what was expected; for example, soft x-rays (aka EUV) were in the semiconductor roadmap as early as 1994 since optical resolution was not expected for sub-100nm features. However, steady improvements and innovations such as Excimer laser sources and immersion photolithography have allowed some manufacturers to build 22nm CMOS SOCs with single-exposure optical lithography. With the transition from random complex 2D shapes to regular 1D-patterns at 28nm, the "lines and cuts" approach can extend CMOS logic to at least the 7nm node. The spacer double patterning for lines and optical cuts patterning is expected to be used down to the 14nm node. In this study, we extend the scaling to 18nm half-pitch which is approximately the 10-11nm node using spacer pitch division and complementary e-beam lithography. For practical reasons, E-Beam lithography is used as well to expose the "mandrel" patterns that support the spacers. However, in a production mode, it might be cost effective to replace this step by a standard 193nm exposure and applying the spacer technique twice to divide the pitch by 3 or 4. The Metal-1 "cut" pattern is designed for a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops. Since the final conductor is defined by a Damascene process, the "cut" patterns become islands of resist blocking hard-mask trenches. The shapes are often small and positioned on a dense grid making this layer to be the most critical one. This is why direct-write e-beam patterning, possibly using massively parallel beams, is well suited for this task. In this study, we show that a conventional shaped beam system can already pattern the 11nm node Metal-1 layer with reasonable overlay margin. The combination of design style, optical lithography plus pitch-division, and e-beam lithography appears to provide a scaling path far into the future.

Proceedings Article | 21 March 2012 Paper

Combined dose and geometry correction (DMG) for low energy multi electron beam lithography (5kV): application to the 16nm node

Luc Martin, Serdar Manakli, Sebastien Bayle, Jérôme Belledent, Sebastien Soulan, Pablo Wiedemann, Abdi Farah, Patrick Schiavone

Proceedings Volume 8323, 83231W (2012) https://doi.org/10.1117/12.916064

KEYWORDS: Metals, Electron beam lithography, Logic, Electroluminescence, Lithography, Optical lithography, Semiconducting wafers, Maskless lithography, Data modeling, Modulation

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Lithography faces today many challenges to meet the ITRS road-map. 193nm is still today the only existing industrial option to address high volume production for the 22nm node. Nevertheless to achieve such a resolution, double exposure is mandatory for critical level patterning. EUV lithography is still challenged by the availability of high power source and mask defectivity and suffers from a high cost of ownership perspective. Its introduction is now not foreseen before 2015. Parallel to these mask-based technologies, maskless lithography regularly makes significant progress in terms of potential and maturity. The massively parallel e-beam solution appears as a real candidate for high volume manufacturing. Several industrial projects are under development, one in the US, with the KLA REBL project and two in Europe driven by IMS Nanofabrication (Austria) and MAPPER (The Netherlands). Among the developments to be performed to secure the takeoff of the multi-beam technology, the availability of a rapid and robust data treatment solution will be one of the major challenges. Within this data preparation flow, advanced proximity effect corrections must be implemented to address the 16nm node and below. This paper will detail this process and compare correction strategies in terms of robustness and accuracy. It will be based on results obtained using a MAPPER tool within the IMAGINE program driven by CEA-LETI, in Grenoble, France. All proximity effects corrections and the dithering step were performed using the software platform Inscale® from Aselta Nanographics. One important advantage of Inscale® is the ability to combine both model based dose and geometry adjustment to accurately pattern critical features. The paper will focus on the advantage of combining those two corrections at the 16nm node instead of using only geometry corrections. Thanks to the simulation capability of Inscale®, pattern fidelity and correction robustness will be evaluated and compared between the correction strategies. This work will be lead on the most critical layers of the 16nm integrate circuits layouts which are contact and metal 1. Finally the aim of this paper is to demonstrate that a complete data preparation flow including advanced proximity effects corrections, simulation and verification capabilities is available for the maskless lithography at the 16nm node and below, through the direct write version of Inscale®. This data preparation platform is already in use in several laboratories for direct write processes.

Proceedings Article | 4 April 2011 Paper

EBPC for multi-beams low kV electron projection lithography

Jérôme Belledent, Sébastien Soulan, Laurent Pain

Proceedings Volume 7970, 79701B (2011) https://doi.org/10.1117/12.879424

KEYWORDS: Semiconducting wafers, Point spread functions, Line edge roughness, Calibration, Modulation, Monte Carlo methods, Electron beam lithography, Projection lithography, Printing, Optical proximity correction

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Proceedings Article | 24 March 2009 Paper

An inverse ellipsometric problem for thin film characterization: comparison of different optimization methods

Ayşe Akbalık, Sébastien Soulan, Jean-Hervé Tortai, David Fuard, Issiaka Kone, Jérôme Hazart, Patrick Schiavone

Proceedings Volume 7272, 72723S (2009) https://doi.org/10.1117/12.814118

KEYWORDS: Thin films, Refractive index, Metrology, Inspection, Process control, Optical lithography, Current controlled current source, Spectroscopy, Polymer thin films, Polymers

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Proceedings Article | 18 June 2007 Paper

In-line etching process control using dynamic scatterometry

Sébastien Soulan, Maxime Besacier, Tanguy Leveder, Patrick Schiavone

Proceedings Volume 6617, 661713 (2007) https://doi.org/10.1117/12.726197

KEYWORDS: Scatterometry, Inverse problems, Databases, Metrology, Data acquisition, Process control, Polarization, Reconstruction algorithms, Data modeling, Visualization

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Proceedings Article | 5 April 2007 Paper

Real-time profile shape reconstruction using dynamic scatterometry

Sébastien Soulan, Maxime Besacier, Tanguy Leveder, Patrick Schiavone

Proceedings Volume 6518, 65180W (2007) https://doi.org/10.1117/12.712015

KEYWORDS: Scatterometry, Metrology, Databases, Inverse problems, Data acquisition, Critical dimension metrology, Polarization, Visualization, Atomic force microscopy, Process control

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Showing 5 of 8 publications

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