With continuous shrink in feature dimensions, overlay tolerance for fabrication of transistors is getting more stringent. Achieving good overlay is extremely critical in getting good yield in HVM environment. It is widely understood that good alignment during exposure is critical for better on product overlay . Conventional methods to choose alignment marks on ASML scanners are based on comparing alignment key performance indicators (KPIs) including signal quality, grid repeatability, etc. It is possible that even with good alignment KPIs, OPO is still impacted. In this paper, we propose aspects that need to be monitored to choose proper alignment marks. LIS (Litho In-Sight) alignment, Ideal overlay/APC parameter signatures are used to determine and validate wafer alignment. LIS alignment ‘Target and Profile selection’ analysis enables us to determine best alignment strategy between multiple strategies/marks based on overlay measurements. Analysis includes examining wafer to wafer OPO variation which is key indicator for alignment robustness. Varying overlay parameters within lot would indicate either large process instability or alignment mark signal instability. It is possible that alignment marks depending on their segmentation can be very differently impacted with the process. Ideal overlay/APC signature stability indicates healthy process and wafer alignment. Having similar APC signatures at corresponding layers would mean that there is no major process or alignment issue.
The imaging performances of XY linear and TE Azimuthal polarization were compared by thin mask
approximation and rigorous 3D mask simulation. The simulations were performed for 40nm and 44nm half pitch patterns
with a hyper NA (1.35) system. Each polarization state was assumed to have a parametric DOP (degree of polarization)
value that was set to 0.95. Rotated dipole illuminators of several angles were used for the associated tilted patterns to see
the imaging impact by IPS (intensity in the preferred state of polarization) change in the process with XY linear
polarization that has a fixed angle of polarization. The difference in performance between two polarization modes were
compared by NILS and DOF margin. Additionally, the imaging quality of BIM (binary intensity mask) with polarization
beam was studied to that of att-PSM at given process conditions. Two types of available BIM masks of different
thickness were applied to simulation to understand 3D mask simulation impact on the imaging contrast and process
margin. The estimation of two-diffraction beam balance was performed to explain the imaging simulation as well. The
polarization sensitivities of NILS and CD change by DOP were found for each feature with given exposure conditions.
The main purpose of this study is to understand how much overestimation or underestimation of conventional thin mask
simulation could be combined in the process simulation by comparing rigorous 3D mask consideration.
As a design rule shrink down aggressively, various RETs (Resolution Enhancement Technology) have been
developed to extend the resolution limits of lithography. Until now, next generation lithography has been focused on
EUV technology. But no one can assure when EUV will be implemented. So, we must develop new technology with
current immersion tool to catch up with aggressive design rule. One of those is DPT (Double Patterning Technology),
however there are also many challenges to overcome such as patterning, overlay, hard mask etch and so on. The most
critical issue would be overlay, because it affects CD (Critical dimension) uniformity directly. Therefore, overlay
control is very important between 1<sup>st</sup> DP layer and 2<sup>nd</sup> DP layer. We utilized ArF immersion scanners for this experiment.
In this paper, DP process flow, hard mask film dependency, align method dependency, efforts of new align key design
and direct align analysis in DP overlay will be reported to understand and get better overlay accuracy than tool
specification. It is needed to be verified that how much they take an effect on improving the DP overlay. Continuously
we can conclude that most efforts in DPT should be focused on overlay control issue.
This paper describes the interesting performance for KrF excimer laser lithography at low k1 process in Rayleigh criteria. For 0.15 micrometer lithography process, the experiments have been performed by using resolution enhancement techniques (RET) such as phase shift masks (PSM), off-axis illumination (OAI), 0.63 high NA, and high contrast resist. Especially for the gate level CD control, we have investigated the thin film interference effects of oxide, resist and BARC thickness variation by simulation and experimental. Also, we have experimentally compared the CD control performance and the process window with oxide thickness variation on actual device wafers, because the oxide thickness variation enhances thin film interference effects. Finally, we determined the most suitable conditions for providing sufficient protection against reflection by controlling the substrate film thickness. Furthermore, requirements for 0.15 micrometer gate level CD control are discussed.
The Wafer-Induced-Shift (WIS) is the overlay measurement error due to the reflection trick of the metal film by Physical Vapor Deposition, specially sputtering. The WIS happens to the wide open type mark because this sputtering method can cause a non-symmetric edge deposition by the self-shadowing of mark depth. But the marks with a wide width and space, which are currently used in the industry, have not detected the WIS. It is the modification of overlay measurement mark that has to be primarily improved to solve this problem. So we suggest the new methodology using the overlay mark with the narrow space. The concept of this mark is to use the geometrical property of deposition and detect the optical contrast signal of the space-type mark instead of the edge contrast signal of wide bar-type mark. This will reduce the non-symmetric deposition property by the self-shadowing. In this paper, we conformed the WIS using the overlay errors after and before etching film, and reported the effectiveness of our new mark by using the sputtered Pt film being one of the electrodes of BST capacitor. Several marks with a space 0.2 micrometer up to 0.5 micrometer were examined for the various thicknesses of the film by comparing the overlay measuring error between the standard mark and the new mark, and correlating the degree of the metal filing into the narrow space of overlay mark with the wafer scale factor. From the experimental results, we can find that the major component of WIS is the wafer magnification factor, and the new mark had a good feasibility for the WIS and might be called the WIS-free mark. Additionally we will discuss more details of our experimental results.