This paper presents the physical device modeling of a Si/Si<sub>1-x</sub>Ge<sub>x</sub> multi-quantum well (MQW) detector to optimize the Ge content in the Si/Si<sub>1-x</sub>Ge<sub>x</sub> well required to enhance thermal sensitivity for a potential microbolometer application. The modeling approach comprises a self-consistent coupled Poisson-Schroedinger solution in series with the thermionic emission theory at the Si/Si<sub>1-x</sub>Ge<sub>x</sub> heterointerface and quantum confinement within the Si/Si<sub>1-x</sub>Ge<sub>x</sub> MQW. The integrated simulation environment developed in Sentauruas WorkBench (SWB) TCAD is employed to investigate the transfer characteristics of the device consisting three stacks of Si/Si<sub>1-x</sub>Ge<sub>x</sub> wells with an active area of 17μm x 17μm were investigated and compared with experiment data.
A 32x32 prototype of a digital readout IC (DROIC) for medium-wave infrared focal plane arrays (MWIR IR-FPAs) is presented. The DROIC employs in-pixel photocurrent to digital conversion based on a pulse frequency modulation (PFM) loop and boasts a novel feature of off-pixel residue conversion using 10-bit column SAR ADCs. The remaining charge at the end of integration in typical PFM based digital pixel sensors is usually wasted. Previous works employing in-pixel extended counting methods make use of extra memory and counters to convert this left-over charge to digital, thereby performing fine conversion of the incident photocurrent. This results in a low quantization noise and hence keeps the readout noise low. However, focal plane arrays (FPAs) with small pixel pitch are constrained in pixel area, which makes it difficult to benefit from in-pixel extended counting circuitry. Thus, in this work, a novel approach to measure the residue outside the pixel using column -parallel SAR ADCs has been proposed. Moreover, a modified version of the conventional PFM based pixel has been designed to help hold the residue charge and buffer it to the column ADC. In addition to the 2D array of pixels, the prototype consists of 32 SAR ADCs, a timing controller block and a memory block to buffer the residue data coming out of the ADCs. The prototype has been designed and fabricated in 90nm CMOS.
A prototype of a readout IC (ROIC) designed for use in high temperature coefficient of resistance (TCR) SiGe microbolometers is presented. The prototype ROIC architecture implemented is based on a bridge with active and blind bolometer pixels with a capacitive transimpedance amplifier (CTIA) input stage and column parallel integration with serial readout. The ROIC is designed for use in high (≥ 4 %/K) TCR and high detector resistance Si/SiGe microbolometers with 17x17 μm<sup>2</sup> pixel sizes in development. The prototype has been designed and fabricated in 0.25- μm SiGe:C BiCMOS process.