Proc. SPIE. 5042, Design and Process Integration for Microelectronic Manufacturing
KEYWORDS: Statistical analysis, Manufacturing, Process control, Transistors, Field effect transistors, Statistical modeling, System on a chip, Device simulation, Instrument modeling, Design for manufacturability
Device scaling increases the impact of within-die variation or mismatch on the performance and yield of many important components of System on Chip (SoC) designs. This has created a need for accurate characterization, modeling, and simulation of mismatch. This paper provides a brief overview of the recent progress in these areas along with an example illustrating the application of these techniques to
Design for Manufacturability (DFM) of Ultra Deep Submicron (UDSM) technologies.
Small feature sizes and reduced tolerances of state-of-the-art microelectronic devices make them extremely sensitive to manufacturing variations. This paper describes two approaches dealing with manufacturing variations: process control and statistical design for manufacturability. Process control seeks to reduce the variability of each process module and statistical design seeks to minimize the impact of the variability. An example illustrates the use of process control to minimize variability. Then, a novel approach for statistical design and its application to statistical optimization of deep submicron CMOS is described. This approach is based on a Markov representation of a process flow that captures the sequential and stochastic nature of semiconductor manufacturing. Using this approach we have been able to predict the variability in device performance for a number of process flows. Transistor designs and process flows optimized using this approach show lower variation in key device performances on fabrication.
An advanced multivariable off-line process control system, which combines traditional Statistical Process Control (SPC) with feedback control, has been applied to the CVD tungsten process on an Applied Materials Centura reactor. The goal of the model-based controller is to compensate for shifts in the process and maintain the wafer state responses on target. In the present application the controller employs measurements made on test wafers by off-line metrology tools to track the process behavior. This is accomplished by using model- bases SPC, which compares the measurements with predictions obtained from empirically-derived process models. For CVD tungsten, a physically-based modeling approach was employed based on the kinetically-limited H2 reduction of WF6. On detecting a statistically significant shift in the process, the controller calculates adjustments to the settings to bring the process responses back on target. To achieve this a few additional test wafers are processed at slightly different settings than the nominal. This local experiment allows the models to be updated to reflect the current process performance. The model updates are expressed as multiplicative or additive changes in the process inputs and a change in the model constant. This approach for model updating not only tracks the present process/equipment state, but it also provides some diagnostic capability regarding the cause of the process shift. The updated models are used by an optimizer to compute new settings to bring the responses back to target. The optimizer is capable of incrementally entering controllables into the strategy, reflecting the degree to which the engineer desires to manipulates each setting. The capability of the controller to compensate for shifts in the CVD tungsten process has been demonstrated. Targets for film bulk resistivity and deposition rate were maintained while satisfying constraints on film stress and WF6 conversion efficiency.