Wafer-to-wafer bonding techniques, such as anodic bonding or high temperature silicon direct fusion bonding, have been in development since the late 1960's and became key technologies for MEMS manufacturing. Plasma assisted wafer bonding is an emerging method offering several advantages over traditional bonding techniques. This technology was first discovered and patented in the early 1990's and has been used in SOI production for the past five years. Now plasma activation benefits are being used to enable 3D integration and advanced MEMS device fabrication and packaging. The main advantage of plasma assisted bonding is that high strength direct bonds between substrates, like Si, glass or polymers, can be achieved already below 300°C.
Wafer bonding became a key technology in various MEMS devices manufacturing. In this respect, wafer bonding is a
very important technology as far as it enables not only 3D structure building but also wafer level packaging.
Plasma activated wafer bonding is a surface activation method in which by applying a plasma treatment to the wafers
prior to bringing them in contact for bonding, the surface chemistry can be tailored in order to obtain maximum bond
strength for low temperature thermal annealing. A major advantage of this process is that it makes possible some
bonding applications which are not possible using standard bonding processes due to different materials characteristics
(e.g. high thermal mismatch of the two bonding partners, low Tg for polymer bonds, etc.)
Plasma activated bonding was successfully applied for different types of materials: silicon, compound semiconductors,
oxides and polymers (e.g. PMMA). The present paper presents experimental results demonstrating the benefits of this
new technology and shows examples on how plasma activated wafer bonding can be an alternative to standard wafer
Wafer level packaging, as well as, chip to wafer bonding has become reliable techniques for MOEMS and MEMS packaging. The main advantage of wafer level processing includes economy of scale and high throughputs. This requires high yielding wafers and a high degree of reproducibility. When these criteria cannot be met, chip to wafer packaging offers an intermediate solution to address the known-good-die concerns. A variety of packaging methods have come to fruition lately as the result of earnest research efforts. Many of these techniques focus on low temperature processing to meet the demands of nanotechnology and integrated materials and systems. Almost categorically, the miniaturization of devices has led to a need for reduced temperature processing to control thermal expansion, dimensional stability, material compatibility, and inclusion of processing circuits. Novel devices made from hot embossed plastics or heterostructures of compound semiconductors require new fabrication and packaging methods. Several wafer bonding options are available ranging from glass seals, low temperature metal based systems, plasma activated direct bonding techniques, and plastic to plastic bonding methods. Critical control of temperature profiles, applied force uniformity and surface preparation give the packaging engineer a wide range of choices for successful device packaging. Prior to 1st level packaging efforts engineered starting materials in the form of laminated substrates can greatly assist in process simplification. The following article describes methods and techniques to create starting materials and use these advanced substrates to the fullest extent for simplified device fabrication. The bonding and patterning techniques use in the front end are also the basis for packaging techniques needed to utilize new methods for wafer level packaging and chip to wafer bonding methods.
The old adage "Work Smarter, Not Harder" is certainly applicable in today's competitive marketplace for Optical MEMS. In order to survive the current economic conditions, high volume manufacturers must get optimum performance and yield from each design and manufactured component. Wafer bonding, and its numerous variants, is entering mainstream production environments by providing solutions throughout the production flow. For example, SOI (silicon on insulator) and other laminated materials such as GaAs/Si are used as cost effective alternatives to molecular epitaxy methods for Bragg mirrors, rf resonators, and hybrid device fabrication. Temporary wafer bonding is used extensively to allow fragile compound semiconductors to be attached to rigid support wafers. This allows for front side and backside processing with a reduction in wafer breakage and increases in thickness uniformity results after backgrind operations. Permanent wafer bonding is used to attach compound semiconductors to each other or silicon to completely integrate optical components and logic or MEMS components. Permanent hermetic sealing is used for waveguide formation and, when combined with vacuum sealing, higher performance is achieved for RF resonators. Finally, many of the low temperature solders and eutectic alloys are finding application in low temperature wafer-to-wafer level packaging of optical devices to ceramic packages. Through clever application of these bonding methods, throughput increases and reduction in fabrication complexity givs a clear edge in the market place. This presentation will provide guidelines and process overviews needed to adopt wafer-to-wafer bonding technologies into the high volume-manufacturing environment.