Challenges in block levels due to the dilemma of cost control and under-layer effects have been addressed in several papers already, and different approaches to solve the issue have been addressed. Among the known approaches, developable BARC and under-layer aware modeling are the most promising. However, in this paper we will discuss and explain the limitation inefficiency of both methods. In addition, as more block levels are employing etching step, the under-layer dependent etch behavior that we see in some of the block levels is also discussed. All these place great challenges for block level process development. We discuss here possible solutions/improvements including: developable BARC (dBARC) thickness optimization for specific under layers; Simplified model based corrections for lith and etch. This work was performed at the IBM Microelectronics Div, Semiconductor Research and Development Center, Hopewell Junction, NY 12533
Low-k 1 lithography results in features that suffer from poor lithographic yield in the presence of process variation. The problem is especially pronounced for lower-level metals used for local routing, where bi-directionality and tight pitches give rise to lithography unfriendly layout patterns. However, there exists inherent unutilized flexibility in design shapes, e.g., one can modify such wires without significantly affecting design behavior. We develop two different techniques to simultaneously modify mask and design shapes during optical proximity correction (OPC) to improve lithographic yield of low-level metal layers. The methods utilize image slope information, which is available during OPC image simulations at no extra cost, as a measure of lithographic process window. We first propose a method that identifies fragments with low normalized image log slope (NILS) and then use this NILS information to guide dynamic target modification between iterations of OPC. The method uses a pre-characterized lookup table to assign a different magnitude of local target correction to different NILS bins. Next we develop an optimization flow where we derive a cost function that maximizes both contour fidelity and robustness to drive our simultaneous mask and target optimization (SMATO) method. We develop analytical equations to predict the cost for a given mask and target modification and use a fast algorithm to minimize this cost function to obtain an optimal mask and target solution. Our experiments on sample 1× (M1) layouts show that the use of SMATO reduces the process manufacturability index (PMI) by 15.4% compared with OPC, which further leads to 69% reduction in the number of layout hotspots. Additionally, such improvement is obtained at low average runtime overhead (5.5%). Compared with process window optical proximity correction (PWOPC), we observe 4.6% improvement in PMI at large (2.6× ) improvement in runtime.
Conventional resolution enhancement techniques (RET) are becoming increasingly inadequate at addressing the challenges of sub-wavelength lithography. In particular, features show high sensitivity to process variation in low-k<sub>1</sub> lithography. While advanced mask optimization techniques such as process window optical proximity correction (PWOPC) exist to address this, they modify electrical properties of shapes in a way that is incommunicable to the designer. A more design-aware approach for improving printability is to perform retargeting, which is a modification of target layout shapes to improve their process window. Retargeting can be performed rule-based or model-based. The former has fast runtime but is not a scalable technique since rules cannot cover the entire search space of two-dimensional shape configurations, especially with technology scaling. The latter provides more coverage of complex 2-D optical interactions compared to rules, but suffers from high runtime and inability to communicate modified design intent back to the designer. In this paper, we explore an alternative approach to retargeting which overcomes the drawbacks of both these methods. We develop a target optimization method based on knowledge of source and the diffraction pattern of the layout. We demonstrate that target optimization can be performed at fast runtime using just the Fourier transform of the layout. This approach is more scalable than rule-based retargeting, but also allows communication of modified design intent by integration into extraction tools.
The move to low-k1 lithography makes it increasingly difficult to print feature sizes that are a small fraction of the wavelength of light. With further delay in the delivery of extreme ultraviolet lithography, these difficulties will motivate the research community to explore increasingly broad solutions. We propose that there is significant research potential in studying the essential premise of the design/manufacturing handoff paradigm. Today this premise revolves around design rules that define what implementations are legal, and raw shapes, which define design intent, and are treated as a fixed requirement for lithography. In reality, layout features may vary within certain tolerances without violating any design constraints. The knowledge of such tolerances can help improve the manufacturability of layout features while still meeting design requirements. We propose a methodology to convert electrical slack in a design to shape slack or tolerances on individual layout shapes. We show how this can be done for two important implementation fabrics: (a) cell-library-based digital logic and (b) static random access memory. We further develop a tolerance-driven optical proximity correction algorithm that utilizes this shape slack information during mask preparation to ensure that all features prints within their shape slacks in presence of lithographic process variations. Experiments on 45 nm silicon on insulator cells using accurate process models show that this approach reduces postlithography delay errors by 50%, and layout hotspots by 47% compared to conventional methods.
Conventional resolution enhancement techniques (RET) are becoming increasingly inadequate at addressing
the challenges of subwavelength lithography. In particular, features show high sensitivity to process variation in
low-k1 lithography. Process variation aware RETs such as process-window OPC are becoming increasingly
important to guarantee high lithographic yield, but such techniques suffer from high runtime impact. An
alternative to PWOPC is to perform retargeting, which is a rule-assisted modification of target layout shapes to
improve their process window. However, rule-based retargeting is not a scalable technique since rules cannot
cover the entire search space of two-dimensional shape configurations, especially with technology scaling. In
this paper, we propose to integrate the processes of retargeting and optical proximity correction (OPC). We
utilize the normalized image log slope (NILS) metric, which is available at no extra computational cost during
OPC. We use NILS to guide dynamic target modification between iterations of OPC. We utilize the NILS
tagging capabilities of Calibre TCL scripting to identify fragments with low NILS. We then perform NILS
binning to assign different magnitude of retargeting to different NILS bins. NILS is determined both for width,
to identify regions of pinching, and space, to locate regions of potential bridging. We develop an integrated flow
for 1x metal lines (M1) which exhibits lesser lithographic hotspots compared to a flow with just OPC and no
retargeting. We also observe cases where hotspots that existed in the rule-based retargeting flow are fixed using
our methodology. We finally also demonstrate that such a retargeting methodology does not significantly alter
design properties by electrically simulating a latch layout before and after retargeting. We observe less than 1%
impact on latch Clk-Q and D-Q delays post-retargeting, which makes this methodology an attractive one for use
in improving shape process windows without perturbing designed values.
Double exposure techniques are an economically viable method for extending the life of the current 193nm
wavelength immersion lithography techniques into future generations of semiconductor scaling. One popular
example of double exposure is the use of double dipole illumination, where the X and Y dipoles are separately
optimized for vertical and horizontal features respectively. The primary challenge in such double exposure
techniques lies in the process of target layout decomposition into patterns that can be optimally printed using their
respective source. Current approaches for decomposition are rule-based. They suffer from the drawbacks of
scalability, rule count explosion and inability to guarantee sufficient yield in the presence of process variation.
Further, rules are characterized specific to sources and are relatively easy to develop for dipoles, but far more
difficult to develop for more complex sources such as used in source mask optimization (SMO). Decomposed
target layouts have to further undergo optical proximity correction (OPC) in order to be converted to a mask for
use in manufacturing. In this paper, we propose a novel approach which integrates the processes of decomposition
and optical proximity correction. We preclude the intermediate target decomposition stage. Instead, we directly
optimize the masks for both exposures simultaneously in order to obtain a wafer image that both closely matches
the target layout and is also robust to process variation. For this purpose, we define a lithographic cost function
that is a weighted sum of intensity error and intensity slope. We develop methods to analytically predict the
change in this cost function due to movement of fragments on each mask. We then utilize a gradient-descent
algorithm for fragment movement to minimize the cost function. Since our methodology is based on the
knowledge of the SOCS decomposition kernels, it is not restricted to dipoles alone, but can be utilized for any
complex sources for which such kernels are known. Our experiments on 1x metal (M1) show significant
improvement in layout process window compared to traditional rule-based decomposition methods.
Chip performance and yield are increasingly limited by systematic and random variations introduced during wafer
processing. Systematic variations are layout-dependent and can be broadly classified as optical or non-optical in nature.
Optical effects have their origin in the lithography process including mask, RET, and resist. Non-optical effects are
layout-dependent systematic variations which originate from processes other than lithography. Some examples of nonoptical
effects are stress variations, well-proximity effect, spacer thickness variations and rapid thermal anneal (RTA)
variations. Semiconductor scaling has led to an increase in the complexity and impact of such effects on circuit
parameters. A novel technique for dataprep called electrically-driven optical proximity correction (ED-OPC) has been
previously proposed which replaces the conventional OPC objective of minimization of edge placement error (EPE) with
an electrical error related cost function. The introduction of electrical objectives into the OPC flow opens up the
possibility of compensating for electrical variations which do not necessarily originate from the lithographic process. In
this paper, we propose to utilize ED-OPC to compensate for optical as well as non-optical effects in order to mitigate
circuit-limited variability and yield. We describe the impact of non-optical effects on circuit parameters such as
threshold voltage and mobility. Given accurate models to predict variability of circuit parameters, we show how EDOPC
can be leveraged to compensate circuit performance for matching designer intent. Compared to existing
compensation techniques such as gate length biasing and metal fills, the primary advantage of using ED-OPC is that the
process of fragmentation in OPC allows greater flexibility in tuning transistor properties. The benefits of using ED-OPC
to compensate for non-optical effects can be observed in reduced guard-banding, leading to less conservative designs. In
addition, results show a 4% average reduction in spread in timing in compensating for intra-die threshold voltage
variability, which potentially translates to mitigation of circuit-limited yield.
Yield loss due to process variations can be classified as catastrophic or parametric. Parametric variations can further
be random or systematic in nature. Systematic parametric variations are being projected as a major yield limiter in sub-
65nm technologies. Though several models exist to describe process-induced parametric effects in layouts, there is no
existing design methodology to study the variational (across process window) impact of all these effects simultaneously.
In this paper, we present a methodology for analyzing multiple process-induced systematic and statistical layout
dependent effects on circuit performance. We describe physical design models used to describe four major sources of
parametric variability - lithography, stress, etch and contact resistance - and their impact on device properties. We then
develop a methodology to determine variability in circuit performance based on integrating the above device models
with a circuit simulator like SPICE. A circuit simulation engine for 45nm SOI devices is implemented, which shows the
extent of the impact of layout-dependent systematic variations on circuit parameters like delay and power. Based on the
analysis, we demonstrate that all systematic effects need to be simultaneously included to match the hardware data. We
believe a flow that is capable of understanding process-induced parametric variability will have major advantages in
terms of improving physical design and yield in addition to reducing design to hardware miscorrelations and
advantages in terms of diagnosis and silicon debug.
Existing optical proximity correction tools aim at minimizing edge placement errors (EPE) due to the optical and resist
process by moving mask edges. However, in low-k1 lithography, especially at 45nm and beyond, printing perfect
polygons is practically impossible to achieve in addition to incurring prohibitively high mask complexity and cost. Given
the impossibility of perfect printing, we argue that aiming to reduce the error of electrical discrepancy between the ideal
and the printed contours is a more reasonable strategy. In fact, we show that contours with non-minimal EPE may result
in closer match to the desired electrical performance.
Towards achieving this objective, we developed a new electrically driven OPC (ED-OPC) algorithm. The tool combines
lithography simulation with an accurate contour-based model of shape electrical behavior to predict the on/off current
through a transistor gate. The algorithm then guides edge movements to minimize the error in current, rather than in
edge placement, between current values for printed and target shapes. The results on industrial 45nm SOI layouts using
high-NA immersion lithography models show up to a 5% improvement in accuracy of timing over conventional OPC,
while at the same time showing up to 50% reduction in mask complexity for gate regions. The results confirm that better
timing accuracy can be achieved despite larger edge placement error.