A simple analytical model is developed to estimate the power loss and time delay in photonic integrated circuits fabricated
using SOI standard wafers. This model is simple and can be utilized in physical verification of the circuit layout to verify
its feasibility for fabrication using certain foundry specifications. This model allows for providing new design rules for the
layout physical verification process in any electronic design automation (EDA) tool. The model is accurate and compared
with finite element based full wave electromagnetic EM solver. The model is closed form and circumvents the need to
utilize any EM solver for verification process. As such it dramatically reduces the time of verification process and allows
fast design rule check.
Double Patterning (DP) is still the most viable lithography option for sub-22nm nodes. The two main types of DP are Litho Etch Litho Etch (LELE) and Self-Aligned Double Patterning (SADP). Of those two, SADP has the advantage of lower sensitivity to overlay error. However SADP imposes a lot of restrictions on the layout. One of the ways to do SADP decomposition is to use an LELE decomposer while prohibiting stitches, and to generate mandrel and trim masks from LELE masks using some Boolean characterization equations. In this paper, we propose an SADP decomposer based on an LELE decomposer that is used to decide which target polygons are mandrel and which are non-mandrel. However the core of the LELE decomposer has been made SADP-aware, such that it gives less priority to pairs of polygons separated by spacing values that are prohibited by SADP. Then, a mandrel and trim masks generator uses the LELE decomposer output and produces the final mandrel and trim masks. Experimental results show that adding SADPawareness to the core of the decomposer has decreased the average number of coloring conflicts by 38%. The proposed decomposer is faster than the previous SADP decomposition approaches that use Integer Linear Programming (ILP) and Satisfiability (SAT).
To continue scaling the circuit features down, Double Patterning (DP) technology is needed in 22nm technologies and
lower. DP requires decomposing the layout features into two masks for pitch relaxation, such that the spacing between
any two features on each mask is greater than the minimum allowed mask spacing. The relaxed pitches of each mask are
then processed on two separate exposure steps. In many cases, post-layout decomposition fails to decompose the layout
into two masks due to the presence of conflicts.
Post-layout decomposition of a standard cells block can result in native conflicts inside the cells (internal conflict), or
native conflicts on the boundary between two cells (boundary conflict). Resolving native conflicts requires a redesign
and/or multiple iterations for the placement and routing phases to get a clean decomposition. Therefore, DP compliance
must be considered in earlier phases, before getting the final placed cell block.
The main focus of this paper is generating a library of decomposed standard cells to be used in a DP-aware placer. This
library should contain all possible decompositions for each standard cell, i.e., these decompositions consider all possible
combinations of boundary conditions. However, the large number of combinations of boundary conditions for each
standard cell will significantly increase the processing time and effort required to obtain all possible decompositions.
Therefore, an efficient methodology is required to reduce this large number of combinations. In this paper, three different
reduction methodologies are proposed to reduce the number of different combinations processed to get the decomposed
library. Experimental results show a significant reduction in the number of combinations and decompositions needed for
the library processing. To generate and verify the proposed flow and methodologies, a prototype for a placement-aware
DP-ready cell-library is developed with an optimized number of cell views.