The process of resist is of great importance to the resolution of e-beam direct-writing exposure. ZEP520 is an excellent positive e-beam resist, which has high resolution, high sensitivity, high contrast as well as good dry etch resistance. In this paper, the e-beam exposure process of ZEP520 on Si and GaAs substrates and its application in nanoelectrode-pair and single-electron transistor have been studied. On Si substrate, the contrast, sensitivity and resolution of ZEP520 have been investigated in detail, and the influence of exposure dose and resist thickness on the size of ZEP520 patterns has been discussed. The contrast of 425nm-thick ZEP520 on Si is 2.70. The sensitivity of ZEP520 is <5 μC/cm2. The size of ZEP520 lines and circular holes decreases with exposure dose decreasing and thickness increasing. 70 nm wide lines and 110-nm-diameter dots can be exposed on Si substrate using 110 nm thick ZEP520. The flaws of ZEP520 on GaAs can be eliminated by fore-baking the GaAs substrate; and 130 nm wide lines can be exposed on GaAs using ZEP520. In regard to application, a nanoelectrode-pair with a 60 nm space has been fabricated using ZEP520. And a kind of in-plane singe-electron transistor (SET) has also been fabricated on silicon-on-insulator (SOI) substrate, which has a 110 nm wide Si Coulomb island and shows Clear Coulomb staircases in Ids from the Ids-Vds characteristics and differential conductance (dIds/dVds) oscillations from the dIds/dVds-Vds characteristics at 2 K.
The Micro-processing & Nano-technology Laboratory at the Institute of Microelectronics, Chinese Academy of Sciences (CAS), is equipped with a GCA 3600F PG&3696, a JBX 6AII & JBX 5000LS EB, and an ETEC MEBES 4700S EB. For a long time we have been engaged in the research and manufacture on Optical Resolution Enhancement Technology (RET) and E-Beam Direct Writing Technology. In this paper the following technologies will be described: PSM, OPC EBDW,EPC,Match & Mixed Lithography technology. Through the application of RET in optical lithography system, we completed the 0.2 um pattern with the g line and I line light source, which is the necessary preparation for 100nm node with 193nm light source. By means of match & mixed lithography and nanofabrication technology, 20nm-50nm gate CMOS transistor and 100nm gate HEMT are successfully developed.