Small process window in ultra-low k<sub>1</sub> lithography (k<sub>1</sub><0.35) poses difficulties for judgment of the availability of high-end photomasks for preliminary exposure tools for high volume production ramp-up. Also, our previous judgment flow of high-end photomasks availability has several concerns. Therefore, the ultra-low k<sub>1</sub> lithography requires accurate judgment methodologies for high-end photomask availability with short turn-around-time (TAT). In this paper, we propose a new concept concerning hot spot-based judgment flow which consists of two stages for high-end photomask availability. Our proposed flow permits judgment of high-end photomask availability for high volume production ramp-up with short TAT.
Effects of mask CD error on lithography performance are estimated as the metric “dose-MEF”. The mask CD error is classified into three categories in accordance with the spatial frequency (global, local and LER). In the global CD error, the CD is constant within the range where the OPE reaches. The local CD error has the spatial frequency that is nearly equal to OPE range. The LER has very small spatial frequency by comparison with OPE range. The effects of local CD error and LER are estimated by using Monte Carlo Simulation because of randomness. For dense pattern, dose-MEF for local error is half of that for global error. Further, dose-MEF for LER is so small that this effect is negligible. Therefore, specifications for mask CD error must be decided by considering dose-MEF for each category.
A new methodology for a mask quality, flexible mask specifications, is proposed. This methodology consists of two major concepts. One is a <i>flexibly</i> selected pattern to guarantee a mask quality for each device and each level of a device. This pattern, hot spot pattern, is selected using a full chip level lithography simulation. The other is <i>flexibly</i> changeable combination of each tolerance of each error component (e.g. CD mean to target, CD uniformity). A mask quality is judged by not each error component, but a total lithography margin. In this methodology, following two points are important. A hot spot pattern should be correctly selected in terms of having large impact on critical dimension (CD) on wafers. An amount of lithography margin reduction due to mask manufacturing error should be correctly estimated. We have improved this methodology in those two points. Firstly, a hot spot pattern is selected in terms of difference of Dose-MEF factor in addition to a pattern having small lithography margin. A Dose-MEF factor defines as ratio of target exposure shift to mask CD error. A difference of Dose-MEF reduces a common lithography margin with patterns having CD errors. Secondary, we measure all kinds of hot spot patterns directly. A common lithography margin is obtained from Exposure-defocus tree (ED-tree) based on actual measurement data. Applying these improved methodologies to memory device mask with 130nm node, we can obtain a lithography margin precisely in comparison with the previous method.
As feature sizes of semiconductor devices shrink, mask errors have a large impact on critical dimension (CD) variation on a wafer and lead to lithography margin reduction. Observed CD error on a wafer is 2 to 4 times as large as CD error on a mask under the low k1 lithography due to mask CD deviation enhancement factor. Mask errors, e.g. CD uniformity, mean to target error, should be controlled and assessed to prevent CD variation on a wafer and lithography margin reduction. Therefore, assessment of mask quality is a critical step in mask manufacturing.
This paper proposes a methodology for assessment of mask quality, flexible mask specifications. The methodology consists of two major concepts. One is flexibly selected patterns to guarantee mask quality for each device and each level of devices using full-chip level lithography simulation. The other is flexibly changeable combination of each tolerance for each error component. The validity of flexible mask specifications is proved on masks of a 130nm node memory device. Using the flexible mask specifications, we have confirmed that mask-manufacturing yield rises by 20% for masks of a 175nm node memory device compared with the yield of the masks judged by conventional mask specifications.
A methodology for specifying mask quality named flexible mask specifications is proposed. The methodology consists of two major concepts. One is flexibly selected patterns to guarantee mask quality for each device and each level of devices using full-chip level lithography simulation. The other is flexibly changeable combination of each tolerance for each error component. The validity of flexible mask specifications is proved on masks of a 130nm node memory device. Using the flexible mask specifications, we have confirmed that mask manufacturing yield rise up by 20 percent on masks of a 175nm node memory device compared with the yield of the masks judged by conventional mask specifications.
A novel, accurate, one-dimensional process proximity correction method is proposed. The method is based on the relationship between a line width variation and the bias which should be corrected. This relationship is characterized by the Total process proximity-based Correction Factor (TCF) which is defined as the slope of the wafer CD variation curve to the mask design CD under a constant pattern pitch condition. At a TCF greater than 1, patterns should be corrected with values less than the line width deviation. By applying the new PPC method to 0.25 micrometer logic gate patterns, a correction rule table was experimentally obtained. The new PPC mask fabricated with the correction rule exhibited a significant improvement over the conventional correction technique in the logic device.
Critical dimension error on a wafer caused by leaking light through embedded shifter type opaque ring on an i-line attenuated phase-shift mask has been studied. We have produced the mask that includes small pinhole-array pattern as the opaque ring, and confirm that transmittance through the opaque ring depends on pinhole size in good agreement with coherent theory. Our experimental result shows that the leakage must be less than 0.125% in transmittance in order to control resist dimension error less than 0.01 micrometer on a wafer for 0.35 - 0.4 micrometer devices. We have also derived an analytical form to represent leaking light, which shows good fit to the transmittance measurements with the various pinhole size. Then we have estimated the allowable error in phase difference and transmittance of the shifter, and that in pinhole size, applying for this formula. We also discuss the process feasibility for embedded shifter type opaque ring.