We explore various resolution enhancement techniques and investigate their patterning benefits for via patterns of the 3-nm logic node using computational lithography. Simulations are performed by the method of source mask optimization (SMO) using the TachyonTM software. Key assessed process parameters include edge placement error (EPE), overlap process window, image NILS, local CD uniformity and NILS depth of focus (nDOF). Simulation results show that the current mask technology employing the standard Ta-based metallic absorber does not offer enough patterning performance for vias of pitch 40 nm and below. SMO results indicate that high-absorption absorbers give a clear improvement in best-focus shift and pattern placement error while phase-shift masks result in a significant increase of NILS and nDOF. EPE improvement of multiple technologies are also investigated. Novel EUV masks together with advanced imaging with low pupil-filling ratio and curvilinear OPC, combined with highresolution and low-roughness resist and enhanced etch process are among the key enabling technologies to extend EUV single patterning to 3-nm logic via layers.
As nodes progress into the 7nm and below regime, extreme ultraviolet lithography (EUVL) becomes critical for all industry
participants interested in remaining at the leading edge. One key cost driver for EUV in the supply chain is the reflective
EUV mask. As of today, the relatively few end users of EUV consist primarily of integrated device manufactures (IDMs)
and foundries that have internal (captive) mask manufacturing capability. At the same time, strong and early participation
in EUV by the merchant mask industry should bring value to these chip makers, aiding the wide-scale adoption of EUV
in the future. For this, merchants need access to high quality, representative test vehicles to develop and validate their
own processes. This business circumstance provides the motivation for merchants to form Joint Development Partnerships
(JDPs) with IDMs, foundries, Original Equipment Manufacturers (OEMs) and other members of the EUV supplier
ecosystem that leverage complementary strengths. In this paper, we will show how, through a collaborative supplier JDP
model between a merchant and OEM, a novel, test chip driven strategy is applied to guide and validate mask level process
development. We demonstrate how an EUV test vehicle (TV) is generated for mask process characterization in advance
of receiving chip maker-specific designs. We utilize the TV to carry out mask process “stress testing” to define process
boundary conditions which can be used to create Mask Rule Check (MRC) rules as well as serve as baseline conditions
for future process improvement. We utilize Advanced Mask Characterization (AMC) techniques to understand process
capability on designs of varying complexity that include EUV OPC models with and without sub-resolution assist features
(SRAFs). Through these collaborations, we demonstrate ways to develop EUV processes and reduce implementation risks
for eventual mass production. By reducing these risks, we hope to expand access to EUV mask capability for the broadest
community possible as the technology is implemented first within and then beyond the initial early adopters.
As the IC industry moves forward to 7nm or 5nm node, the minimum pitch of back-end-of-line (BEOL) layers could be near 30nm. Extreme ultraviolet (EUV) could be the most cost effective solution for patterning critical metal and via layers. Patterning of the critical layers would need greater than 4x exposures using ArFi lithography, leading to severe cost and yield issues. There are two potential design options, one-dimension (1D) and two-dimension (2D), for metal 1 layer. EUV’s single exposure option offers superior image quality especially for the 2D design style, but scalability of a 2D design is limited by EUV with a fixed numerical aperture (NA). The single exposure of EUV is an appropriate patterning solution for printing a 1D design directly, but maintaining critical dimension uniformity (CDU) of lines and line-ends is a challenge. Scalability of the 1D design is also limited by the single exposure option. The 1D design can be patterned through a spacer film deposition to gain superior line CD control, followed by printing a cut or block pattern to create the line-ends. Since the minimum pitch of cut/block patterns is generally larger than the metal pitch, EUV’s single exposure option has a potential to print the cut/block pattern at smaller pitch and resolution and offers an opportunity to further design shrink. An elongated via design helps design scalability due to an insensitive overlay error contribution to via-to-metal contact area and encroachment.
EUV is considered as the most promising candidate for manufacturing advanced semiconductors at the 32nm HP
technology generation and beyond. It has been demonstrated that the ASML TWINSCAN NXE:3100 is able to print
27nm lines and spaces and 32nm contact holes with NA0.25. Moving forward, higher NA EUV system such as the
ASML TWINSCAN NXE:3300B can generate a higher contrast aerial image due to improved diffractive order
collection efficiency and is expected to achieve a greater percentage of under-exposure or dose reduction via mask
biasing. In this work, we study by simulation the benefit of EUV high NA imaging in the MRC (Mask Rule Check)
trade-offs required to achieve the viable manufacturing solutions for two device application scenarios: 6T-SRAM contact
layer for the logic 14 nm technology node, and 32nm half pitch NAND Flash contact layer. The 3D mask effects versus
Kirchhoff mask for these two applications are also investigated.
For the development of the most cost effective lithographic solutions for the 22nm node, the lithographic process and
relevant requirements on CDU and overlay need to be identified. In this work, 22nm logic SRAM is selected as use case
because FinFET SRAM cells are considered to be a potential successor to conventional planar transistors for 22nm node
chips. We focus on the back-end layers of FinFET SRAM, including metal and contact. Litho solutions simulated under
ideal scanner conditions with the ASML Brion TachyonTM SMO product are shown. This tool co-optimizes a pixilated
freeform source and a continuous transmission gray tone mask based on merit functions of edge placement error. Per
scenario, these simulations result in a set of preferred litho solutions with respective source and mask. These solutions
have to comply with an imaging metric characterized by MEEF and common PW based on typical fab requirements. In a
second step the previously generated solutions are evaluated for CDU analysis using realistic scanner error budget. The
purpose is to predict the CDU performance of scanner, process and reticle in order to identify the major contributors for
every scenario solution.
The fingerprint of optical proximity effect, OPE, is required to develop each process node's optical proximity correction
(OPC) model. The OPC model should work equally well on exposure systems of the type on which the model was
developed and of different type. Small differences in optical and mechanical scanner properties can lead to a different
CD characteristic for a given OPC model. It becomes beneficial to match the OPE of one scanner to the scanner
population in a fab. Here, we report on a matching technique based on measured features in resist employing either CDSEM
or scatterometry. We show that angle resolving scatterometry allows improving the metrology throughput and
repeatability. The sensitivity of the CD as a function of the scanner adjustments and the effect of scanner tuning can be
described more precisely by scatterometry using an identical number of printed features for measurement. In our
example the RMS deviation between the measured and the predicted tuning effect of scatterometry is 0.2 nm compared
to 0.8 nm of CD-SEM allowing to set tighter matching targets.
This work demonstrates a methodology for evaluating the multiple feature error budget of NAND-Flash Gate layer and investigates the process capability of the Double Patterning Technology (DPT) options, LELE and Spacer, for NAND Flash 32nm and below. Since the effective k1 limit for DPT is near 0.14 for dense 1D features, three types of ASML scanners are potential candidates for imaging such devices: XT:1400, XT:1700i and XT:1900i. We will present the results of a simulation evaluation of the DPT process capability of these scanners for NAND-Flash Gate layer with 32nm and 22nm half pitch. The DPT capability involves not only lithography but also the subsequent patterning steps of the selected process flow. Moreover, the pattern sensitivity to scanner parameter variations increases with further scaling. It is therefore crucial to take into account the reasonable budgets of scanner dose, focus and overlay errors as well as the error budgets of film deposition, etch and mask registration. This work will not only evaluate the LELE DPT and Spacer feasibility for the mentioned scanners but also analyze the main contributors of CDU in DPT processes and indicate directions we may follow to improve.
The authors will explore the possible contact hole lithography solutions for the future technology nodes, from 90 nm
down to 32 nm half-pitch (HP) in this paper. The special emphasis will be on the logic application because of the lack of
a strong resolution enhancement technique (RET) for the random hole layouts. The use of illumination optimization,
focus drilling can extend the projection optical lithography down to near 60 nm HP. The adoption of pitch split double
exposure technique is needed to provide a robust manufacturing process window to further extend to around 50 nm HP.
To further shrinking the design rule, a double patterning is need after the pitch split. The pitch split double patterning
technique reaches its limit around 40 - 45 nm HP. The desire to not limit the integrated circuit (IC) design requires the
lithography process k1 to be as high as possible. The random logic contact hole application is well suited for EUV
lithography for 35 nm HP and below because of the high k1 process and a potential for high productivity of a mask based
lithography. The pattern density of contact hole masks would not require a stringent mask defect requirement, and
moreover, the EUV's relatively higher system flare does not have a significant impact on imaging. Actual EUV data and
calibrated simulations will be used to demonstrate that EUV can provide a robust process window.
A procedure for calibrating a resist model iteratively adjusts appropriate parameters until the simulations of the model match the experimental data. The tunable parameters may include the shape of the illuminator, the geometry and transmittance/phase of the mask, light source and scanner-related parameters that affect imaging quality, resist process control and most importantly the physical/chemical factors in the resist model. The resist model can be accurately calibrated by measuring critical dimensions (CD) of a focus-exposure matrix (FEM) and the technique has been demonstrated to be very successful in predicting lithographic performance. However, resist model calibration is more challenging in the low k1 (<0.3) regime because numerous uncertainties, such as mask and resist CD metrology errors, are becoming too large to be ignored. This study demonstrates a resist model calibration procedure for a 0.29 k1 process using a 6% halftone mask containing 2D brickwall patterns. The influence of different scanning electron microscopes (SEM) and their wafer metrology signal analysis algorithms on the accuracy of the resist model is evaluated. As an example of the metrology issue of the resist pattern, the treatment of a sidewall angle is demonstrated for the resist line ends where the contrast is relatively low. Additionally, the mask optical proximity correction (OPC) and corner rounding are considered in the calibration procedure that is based on captured SEM images. Accordingly, the average root-mean-square (RMS) error, which is the difference between simulated and experimental CDs, can be improved by considering the metrological issues. Moreover, a weighting method and a measured CD tolerance are proposed to handle the different CD variations of the various edge points of the wafer resist pattern. After the weighting method is implemented and the CD selection criteria applied, the RMS error can be further suppressed. Therefore, the resist CD and process window can be confidently evaluated using the accurately calibrated resist model. One of the examples simulates the sensitivity of the mask pattern error, which is helpful to specify the mask CD control.
Polarization is becoming very important technology in micro-lithography at the higher NA lithography for much smaller design. The wide and intensive studies to apply the polarization technology into lithography application have been achieved. Source polarization, mask polarization and projection lens polarization could make different printing results compared to non-polarization cases. Especially k1 factor below 0.3 needs aggressive resolution enhancement techniques. Environmental parameters such as mask CD, lens aberration, stray light, image plane deviation and resist characteristic make CD controllability worse in the very low k1 regime. The polarization technology can contribute to getting better imaging performance. This experiment is challenging k1 factor down to 0.29 with the source polarization function. The source polarization effect on real device will be shown through the simulation and actual printing process using 6% attenuated PSM. The related OPC strategy with the polarized source will also be discussed.
As the design rule of device shrinks down, it is difficult to enlarge the process window, especially DOF (Depth of Focus). It has shown good results in resolution issues with short wavelength, high NA aperture and several RET (Resolution Enhancement Technique) like special illuminator and mask techniques and so on. But it needs to be challenged for DOF process window in contact / via process having various pitch and pattern location. It is a key point in sub 100nm process development and product. It is demonstrated that focus scan method is effective for DOF improvement in contact and via layers. Focus Scan method is one of the focus drilling techniques; it is realized to tilt wafer stage so that the same point on the wafer field can be exposed in limited continual focus range using multiple focal planes through the slit of scanner tool. In this study, confirmation was inspected for simulation and wafer evaluation for focus scan effects in view of process feasibility. DOF increased over 50% with focus scan in contact mask process even though there are several issues to be solved and considered. Energy Latitude (EL) decreased a little by image contrast drop, but if we consider the process window for evolution of device, it is relatively enough for process. OPC or Bias tuning is needed for application in contact layer having various pitch and location, and overlay issues are needed to confirm for each illuminator. From these experiments, it is found that DOF margin can easily be enhanced using focus scan method. Also some fine tuning is required to adequately use this method on production devices.