This design case identifies generalizable features of a course-grained reconfigurable FPGA, Chameleon's reconfigurable platform. An FFT is used to identify typical design practices, problems, and solutions in targeting such a platform. This paper focuses on datapath mapping, separating it into functional design and placement of reconfigurable resources. In addition to exploring the design methodology, it analyzes numerical artifacts, demonstrates efficient packing of the data path, and highlights differences from ASIC design.
This paper presents concepts behind the use of the beam propagation method (BPM) to model the vector nature of optical waves, and for wave propagation at wide angles off-axis. The two enhancements have been combined.
The existing computer-aided-design tools in optoelectronics are reviewed and compared. The beam propagation method, the most commonly used method in guided-wave devices, is applied to optical filter design. The simulation result is compared with the published experimental result.
The applicability of large-area full-frame CCD image sensor technology to large optical format aerial reconnaissance applications has been recently demonstrated. The requirements of low-contrast, high-resolution imaging at high frame rates have generated the need for a manufacturable, multitap, small-pitch, wafer-scale CCD image sensor technology. The added requirement of incorporation of electronic motion compensation at the focal plane has generated the need for multisegmented full-frame area array architectures. Characterization results from the newly developed 5040 X 5040 element, eight-tap, full-frame image sensor with multisegmentation for electronic motion compensation are discussed. Experimental determination of resistive-capacitive time constants for metal strapped vertical clock busses on wafer-scale sensors is discussed.
Focal planes constructed of high speed, high resolution CCD image sensors are suitable for airborne reconnaissance applications, but have mainly consisted of linear and TDI array configurations. Until recently large format area arrays have been limited to staring applications, characterized by long integration times and slow readout rates. Large area reconnaissance focal planes require opto-mechanical systems for motion compensation across the imaging plane. A unique CCD architecture has been developed to provide electronic image motion compensation using variable speed vertical clocking segments. This architecture has been applied to very large full frame CCD sensors having 2048 X 2048 and 5040 X 5040 pixel formats.
Reconnaissance systems incorporating solid-state image sensors have advantages over film- based systems in their ability to provide real-time images and transmit digital data to a remote location. In this application area array sensors have advantages over linear and TDI type sensors in eliminating the need for the aircraft to travel in a straight line as is required for 'push broom' imaging. DALSA has previously developed a single output 2048 X 2048 area array which evolved to a four output high speed image sensor suitable for airborne reconnaissance. In this paper we discuss a four output 5120 X 5120 image sensor; this sensor is a prototype for an 8 output imager suitable to replace film recording media for airborne reconnaissance. We review the performance of the existing 5120 X 5120 array and discuss the design modifications implemented on the second generation device to match reconnaissance requirements, improve performance and enhance yield.
A 26.2 million pixel CCD Imager Sensor has been successfully designed and fabricated. The device uses a full frame architecture with 5,120 X 5,120 pixels organization. With a pitch of 12 microns in both dimensions, the overall image zone is 61.44 mm X 61.44 mm. The charge storage capacity of each photosite is greater than 130,000 electrons and the minimum detectable charge is 50 electrons when correlated double sampling is used. The device is also capable of reduced dark current operation of 60 pA/cm<SUP>2</SUP> when operated in the surface inversion mode. The device has four outputs, each of which can operate up to 12 MHz.
Large format charge coupled device area arrays (1 million pixels or more) have proven to be useful in scientific, medical and industrial imaging applications. DALSA has developed a 1024 X 1024 pixel single output, full-frame area array incorporating 3-poly 3-phase buried channel NMOS CCD shift registers and a 10 micrometers X 10 micrometers pixel pitch. The device was fabricated with an additional buried channel implant (notch) in the pixel columns to increase charge storage capacity. In this paper the authors discuss the design and initial performance evaluation of the device. Preliminary measurements of the pixel charge storage capacity indicate 70,000 e- without notch and 140,000 e- with notch. The results indicate that the sensor should be suitable for a variety of applications such as high resolution machine vision, still photography, and scientific imaging.