Mr. Shinichi Hatakeyama Profile

Shinichi Hatakeyama

at Tokyo Electron Kyushu Ltd

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Author

Publications (8)

Proceedings Article | 30 March 2010 Paper

LWR reduction by novel lithographic and etch techniques

Shinji Kobayashi, Satoru Shimura, Tetsu Kawasaki, Kathleen Nafus, Shinichi Hatakeyama, Hideo Shite, Eiichi Nishimura, Masato Kushibiki, Arisa Hara, Roel Gronheid, Alessandro Vaglio-Pret, Junichi Kitano

Proceedings Volume 7639, 763914 (2010) https://doi.org/10.1117/12.846318

KEYWORDS: Line width roughness, Photoresist processing, Etching, Image processing, Extreme ultraviolet lithography, Extreme ultraviolet, Lithography, Image analysis, Coating, Critical dimension metrology

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Proceedings Article | 1 April 2009 Paper

Resist fundamentals for resolution, LER, and sensitivity (RLS) performance tradeoffs and their relation to micro-bridging defects

Benjamin Rathsack, Kathleen Nafus, Shinichi Hatakeyama, Yuhei Kuwahara, Junichi Kitano, Roel Gronheid, Alessandro Vaglio Pret

Proceedings Volume 7273, 727347 (2009) https://doi.org/10.1117/12.814287

KEYWORDS: Line width roughness, Diffusion, Calibration, Extreme ultraviolet lithography, Data modeling, Photoresist processing, Line edge roughness, Polymers, Absorbance, Performance modeling

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Proceedings Article | 18 March 2009 Paper

Investigation of EUV-process sensitivities for wafer-track processing

Neil Bradon, Heiko Weichert, K. Nafus, S. Hatakeyama, J. Kitano, H. Kosugi, K. Yoshihara, M. Goethals, J. Hermans

Proceedings Volume 7271, 727148 (2009) https://doi.org/10.1117/12.814189

KEYWORDS: Semiconducting wafers, Extreme ultraviolet, Extreme ultraviolet lithography, Photoresist processing, Critical dimension metrology, Finite element methods, Double patterning technology, Image processing, Standards development, Lithography

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Proceedings Article | 16 March 2009 Paper

A CDU comparison of double patterning process options using Monte Carlo simulation

Josh Hooge, Shinichi Hatakeyama, Kathleen Nafus, Steven Scheer, Philippe Foubert, Shaunee Cheng, Philippe Leray

Proceedings Volume 7274, 72741U (2009) https://doi.org/10.1117/12.814332

KEYWORDS: Etching, Critical dimension metrology, Monte Carlo methods, Double patterning technology, Photoresist processing, Semiconducting wafers, Dielectrophoresis, Overlay metrology, Calibration, Lithography

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Proceedings Article | 16 March 2009 Paper

Advances and challenges in dual-tone development process optimization

Carlos Fonseca, Mark Somervell, Steven Scheer, Wallace Printz, Kathleen Nafus, Shinichi Hatakeyama, Yuhei Kuwahara, Takafumi Niwa, Sophie Bernard, Roel Gronheid

Proceedings Volume 7274, 72740I (2009) https://doi.org/10.1117/12.814289

KEYWORDS: Image processing, Photoresist processing, Double patterning technology, Photomasks, Optical lithography, Printing, Scanning electron microscopy, Scanners, Manufacturing, Lithography

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Proceedings Article | 7 March 2008 Paper

Image contrast contributions to immersion lithography defect formation and process yield

Ben Rathsack, Josh Hooge, Steven Scheer, Kathleen Nafus, Shinichi Hatakeyama, Hontake Kouichi, Junichi Kitano, Dieter Van Den Heuval, Philippe Leray, Eric Hendrickx, Phillipe Foubert, Roel Gronheid

Proceedings Volume 6924, 69244W (2008) https://doi.org/10.1117/12.772728

KEYWORDS: Line edge roughness, Polymers, Semiconducting wafers, Nanoimprint lithography, Image processing, Immersion lithography, Photoresist processing, Diffusion, Scanning electron microscopy, Reticles

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Proceedings Article | 29 March 2006 Paper

193nm immersion process defect generation and reduction mechanism investigation using analytical methods

Masashi Enomoto, Shinichi Hatakeyama, Takafumi Niwa, Tadatoshi Tomita, Hideharu Kyoda, Junichi Kitano, Satoru Shimura, Tetsu Kawasaki

Proceedings Volume 6153, 61533L (2006) https://doi.org/10.1117/12.656363

KEYWORDS: Thin film coatings, Semiconducting wafers, Contamination, Silicon, Photoresist processing, Spectroscopy, Liquids, Mass spectrometry, Oxygen, Surface roughness

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Proceedings Article | 29 March 2006 Paper

Defectivity reduction by optimization of 193-nm immersion lithography using an interfaced exposure-track system

Michael Carcasi, Shinichi Hatakeyama, Kathleen Nafus, Richard Moerman, Youri van Dommelen, Peter Huisman, Joshua Hooge, Steven Scheer, Philippe Foubert

Proceedings Volume 6153, 61533J (2006) https://doi.org/10.1117/12.656444

KEYWORDS: Photoresist processing, Thin film coatings, Immersion lithography, Scanners, Lithography, Binary data, Standards development, Contamination, Image processing, 193nm lithography

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As the integration of semiconductor devices continues, pattern sizes required in lithography get smaller and smaller. To achieve even more scaling down of these patterns without changing the basic infrastructure technology of current cutting-edge 193-nm lithography, 193-nm immersion lithography is being viewed as a powerful technique that can accommodate next-generation mass productions needs. Therefore this technology has been seriously considered and after proof of concept it is currently entering the stage of practical application. In the case of 193-nm immersion lithography, however, because liquid fills the area between the projection optics and the silicon wafer, several causes of concern have been raised - namely, diffusion of moisture into the resist film due to direct resist-water interaction during exposure, dissolution of internal components of the resist into the de-ionized water, and the influence of residual moisture generated during exposure on post-exposure processing. To prevent these unwanted effects, optimization of the three main components of the lithography system: materials, track and scanner, is required. For the materials, 193nm resist formulation improvements specifically for immersion processing have reduced the leaching and the sensitivity to water related defects, further benefits can be seen by the application of protective top coat materials. For the track component, optimization of the processing conditions and immersion specific modules are proven to advance the progress made by the material suppliers. Finally, by optimizing conditions on the 3^rd generation immersion scanner with the latest hardware configuration, defectivity levels comparable to dry processing can be achieved. In this evaluation, we detail the improvements that can be realized with new immersion specific track rinse modules and formulate a hypothesis for the improvements seen with the rinsing process. Additionally, we show the current status of water induced immersion specific defect reduction using the latest advances in technology.

Showing 5 of 8 publications

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