With the miniaturization of devices, hot spot evaluation of a wide area of a wafer for small change points such as wafer topology is required. DBM (Design Based Metrology) is an effective method for evaluating systematic defects of multiple patterning and EUV lithography. However, it takes a long time to evaluate because it is necessary to acquire a high-SN SEM image captured by low-speed SEM scanning conditions. Therefore, we developed a new pattern matching method of DBM by utilizing deep learning technology. Our proposed method can handle low-SN SEM images captured under high-speed SEM scanning conditions. <p> </p>In the proposed method, we use deep learning to estimate design layout from SEM image, and then perform pattern matching between this estimated design layout and the true design layout. The proposed method is particularly effective for pattern matching of low-SN SEM images and circuit pattern distorted during manufacturing process. It is expected that this method will be advantageous for evaluating mass systematic defects during the process development. Experimental results showed that the proposed method could estimate the design layout from the low-SN SEM image and improve the pattern matching success rate.
With the miniaturization of devices, hot spots caused by wafer topology are becoming a problem in addition to hot spots resulting from design, mask and wafer process, and hot spot evaluation of a wide area in a chip is becoming required. Although DBM (Design Based Metrology) is an effective method for evaluating systematic defects of EUV lithography and multi-patterning, it requires a long time to evaluate because it is necessary to acquire a high-SN SEM image captured by a contour extraction for DBM that can handle low-SN SEM image captured by high-speed SEM scanning conditions.<p> </p> Contour extraction using deep learning possesses high noise immunity and excellent pattern recognition ability, and demonstrates high performance to contour extraction from low SN SEM images and multiple layers pattern ones. The proposed method is composed of annotation operation of SEM image samples, training process using annotation data and SEM image samples, and contour extraction process using the trained outcome. In the evaluation experiment, we confirmed that satisfactory contours are extracted from low SN SEM images and multiple layers pattern ones.
We have developed a new focus measurement method based on analyzing SEM images that can help to control a scanner.
In advanced semiconductor fabrication, rigorous focus control of the scanner has been required because focus error causes a defect.
Therefore, it is essential to ensure focus error are detected at wafer fabrication.
In the past, the focus has been measured using test patterns made outside of the chip by optical metrology system.
Thus, present focus metrology system can’t measure the focus of an arbitrary point in the chip.
The new method enables a highly precise focus measurement of the arbitrary point of the chip based on a focus plane of a reference scanner.
The method estimates the focus amount by analyzing side wall shapes of circuit patterns of SEM images.
Side wall shapes are quantified using multisliced contours extracted from SEM-images high accuracy.
By using this method, it is possible to measure the focus of the arbitrary circuit pattern area of the chip without a test pattern.
We believe the method can contribute to control the scanner and to detect hot spots which appear by focus error.
This new method and the evaluation results will be presented in detail in this paper.
We have developed a highly integrated method of mask and silicon metrology. The aim of this integration
is evaluating the performance of the silicon corresponding to Hotspot on a mask. It can use the mask
shape of a large field, besides. The method adopts a metrology management system based on DBM (Design
Based Metrology). This is the high accurate contouring created by an edge detection algorithm used in mask
CD-SEM and silicon CD-SEM. Currently, as semiconductor manufacture moves towards even smaller
feature size, this necessitates more aggressive optical proximity correction (OPC) to drive the
super-resolution technology (RET). In other words, there is a trade-off between highly precise RET and
mask manufacture, and this has a big impact on the semiconductor market that centers on the mask
business. As an optimal solution to these issues, we provide a DFM solution that extracts 2-dimensional
data for a more realistic and error-free simulation by reproducing accurately the contour of the actual
mask, in addition to the simulation results from the mask data. On the other hand, there is roughness in
the silicon form made from a mass-production line. Moreover, there is variation in the silicon form. For
this reason, quantification of silicon form is important, in order to estimate the performance of a pattern.
In order to quantify, the same form is equalized in two dimensions. And the method of evaluating based
on the form is popular. In this study, we conducted experiments for averaging method of the pattern
(Measurement Based Contouring) as two-dimensional mask and silicon evaluation technique. That is,
observation of the identical position of a mask and a silicon was considered. The result proved its
detection accuracy and reliability of variability on two-dimensional pattern (mask and silicon) and is
adaptable to following fields of mask quality management.
•Discrimination of nuisance defects for fine pattern.
•Determination of two-dimensional variability of pattern.
•Verification of the performance of the pattern of various kinds of Hotspots.
In this report, we introduce the experimental results and the application. We expect that the mask
measurement and the shape control on mask production will make a huge contribution to mask
yield-enhancement and that the DFM solution for mask quality control process will become much more important technology than ever. It is very important to observe the form of the same location of Design,
Mask, and Silicon in such a viewpoint. And we report it about algorithm of the image composition in
We have developed a new concept high-speed and high-resolution color scanner (Blinkscan) using digital camera technology. With our most advanced sub-pixel image processing technology, approximately 12 million pixel image data can be captured. High resolution imaging capability allows various uses such as OCR, color document read, and document camera. The scan time is only about 3 seconds for a letter size sheet. Blinkscan scans documents placed "face up" on its scan stage and without any special illumination lights. Using Blinkscan, a high-resolution color document can be easily inputted into a PC at high speed, a paperless system can be built easily. It is small, and since the occupancy area is also small, setting it on an individual desk is possible. Blinkscan offers the usability of a digital camera and accuracy of a flatbed scanner with high-speed processing.
Now, about several hundred of Blinkscan are mainly shipping for the receptionist operation in a bank and a security.
We will show the high-speed and high-resolution architecture of Blinkscan. Comparing operation-time with conventional image capture device, the advantage of Blinkscan will make clear. And image evaluation for variety of environment, such as geometric distortions or non-uniformity of brightness, will be made.
The Hard X-ray Detector (HXD) is one of the three instruments on the fifth Japanese cosmic X-ray satellite ASTRO-E, scheduled for launch in January 2000. The HXD covers a wide energy range of 10-600 keV, using 16 identical GSO/BGO phoswich-counter modules, of which the low-energy efficiency is greatly improved by adding 2 m-thick silicon PIN diodes. Production of the HXD has been completed and pre-flight calibration is now in progress. The design concept of the HXD sensor, detail of the production process, and a brief summary of the measured performance is reported.
A total and coherent image processing architecture for
G3/G4/ISDN facsimiles is proposed that features high-quality multilevelprocessing by means ofcorrelative area scanning and a softwareoriented processing architecture. This image processing LSI controiler
includes a resolution converter and error diffusion halftone processing circuits in 4000 gates. A semi-superfine scanning mode is evaluated, which will be adopted as a new CCITT G3 optional mode.