It is important to remove image noise properly to measure critical dimension (CD) and roughness values from scanning electron microscope (SEM) images. In order to reduce image noise, the number of electron beam (EB) scans, or frame number, is increased. However, this excess EB irradiation damages the objects being measured and changes their size. In this paper, a new image analysis method is introduced to remove image noise without a typical noise filter. In this method, each image frame is used in a four dimensional array, and several artificial images are generated and edge coordinates are calculated. As a result of this new method, we can separate the line width roughness (LWR) components into process roughness and image noise, and analyze images with lower number of frames with minimal EB damage.<p> </p> The impact of image noise on the accuracy of CD extraction is explained in the section on analysis of variance (ANOVA). The variation is separated as wafer to wafer (WTW), field to field (FTF), die to die (DTD), pattern to pattern (PTP), line width roughness (LWR), and stochastic pattern noise (SPN; which is random variation per a pattern) at this ANOVA. Roughness component from image noise is included in SPN. It is possible to remove the image noise component from SPN by applying this new image analysis method, and it is also possible to discuss the SPN from shot noise of exposure tool or variation of resist material component. ANOVA can put an end to discussion of measurement length of line pattern to know the state of low frequency roughness. LWR component of long wavelength is distributed to PTP and SPN when short patterns are measured. It is important to remove image nose properly and to compare the statistical analysis processed SPN value.
Multi-patterning, like LE and SAMP, has been in production for several years. It is expected to remain a standard in patterning, even in the case where industry adopts EUV photo lithography. As scaling continues, the precision of pattern placement remains challenging.<p> </p> Edge Placement Error (EPE) has been proposed to define the requirements of a patterning process. Many authors have created statistical models for EPE, and gathered statistical data for CD and overlay (OVL), to make predictions about future technology specifications<sup>1-5</sup>. This work makes the following contributions:
Emphasis on large amount (63K) of on-product measurements
Use of ANOVA table to assess the hypothesis that a contender process is better than a POR process To differentiate our work, we have used the stochastic variable IPFE (Interactive Pattern Fidelity Error), which is an indicator to quantify the quality of on-wafer edge placement accuracies in multi-patterning6. In our previous paper, we have studied how overlay, LCDU and pitch walk factor into the IPFE budget<sup>7</sup>. In this work, we focus on experimental verification of the expected relationships between LCDU, overlay and CD variation, applied to the case of SADP (block on spacer):
We re-confirm that population ‘blocks-on-gap’ have a worse IPFE performance than ‘block-on-core’
We determine experimental behavior of IPFE vs line CD, block CD, and overlay (w/o assumption for any model) From this exercise, we can conclude that this IPFE indicator is a robust metric for the managing quality of any integrated patterning scheme.
In the discussion of edge placement error (EPE), we proposed interactive pattern fidelity error (IPFE) as an indicator to judge pass/fail of integrated patterns. IPFE consists of lower and upper layer EPEs (CD and center of gravity: COG) and overlay, which is decided from the combination of each maximum variation. We succeeded in obtaining the IPFE density function by Monte Carlo simulation. In the results, we also found that the standard deviation (σ) of each indicator should be controlled by 4.0σ, at the semiconductor grade, such as 100 billion patterns per die. Moreover, CD, COG and overlay were analyzed by analysis of variance (ANOVA); we can discuss all variations from wafer to wafer (WTW), pattern to pattern (PTP), line edge roughness (LWR) and stochastic pattern noise (SPN) on an equal footing. From the analysis results, we can determine that these variations belong to which process and tools. Furthermore, measurement length of LWR is also discussed in ANOVA. We propose that the measurement length for IPFE analysis should not be decided to the micro meter order, such as >2 μm length, but for which device is actually desired.
In our previous paper dealing with multi-patterning, we proposed a new indicator to quantify the quality of final wafer pattern transfer, called interactive pattern fidelity error (IPFE). It detects patterning failures resulting from any source of variation in creating integrated patterns. IPFE is a function of overlay and edge placement error (EPE) of all layers comprising the final pattern (i.e. lower and upper layers). In this paper, we extend the use cases with Via in additional to the bridge case (Block on Spacer). We propose an IPFE budget and CD budget using simple geometric and statistical models with analysis of a variance (ANOVA). In addition, we validate the model with experimental data. From the experimental results, improvements in overlay, local-CDU (LCDU) of contact hole (CH) or pillar patterns (especially, stochastic pattern noise (SPN)) and pitch walking are all critical to meet budget requirements. We also provide a special note about the importance of the line length used in analyzing LWR. We find that IPFE and CD budget requirements are consistent to the table of the ITRS’s technical requirement. Therefore the IPFE concept can be adopted for a variety of integrated structures comprising digital logic circuits. Finally, we suggest how to use IPFE for yield management and optimization requirements for each process.
Proc. SPIE. 9779, Advances in Patterning Materials and Processes XXXIII
KEYWORDS: Semiconductors, Optical lithography, Etching, Error analysis, Manufacturing, Inspection, Scanning electron microscopy, Process control, Wafer inspection, Plasma etching, Error control coding, Semiconducting wafers, System on a chip, Overlay metrology, Device simulation, Tin
We discuss edge placement errors (EPE) for multi-patterning of Mx critical layers using ArF lithography. Specific focus is placed on the block formation part of the process. While plenty of literature characterization data exist on spacer formation, only limited published data is available on block processes. We analyze the accuracy of placing blocks relative to narrow spacers. Many publications calculate EPE assuming Gaussian distributions for key process variations contributing to EPE. For practical reasons, each contributor is measured on dedicated test structures. In this work, we complement such analysis and directly measure the EPE in product. We perform high density sampling of blocks using CDSEM images and analyze all feature edges of interest. We find that block placement errors can be very different depending on their local design context. Specifically we report on 2 block populations (further called block A and B) which have a 4x different standard deviation. We attribute this to differences in local topography (spacer shape) and interaction with the plasma-etch process design. Block A (on top of the ‘core space’ S1) has excellent EPE uniformity of ~1 nm while block B (on top of ‘gap space’ S2) has degraded EPE control of ~4 nm. Finally, we suggest that the SOC etch process is at the origin on positioning blocks accurately on slim spacers, helping the manufacturability of spacer-based patterning techniques, and helping its extension toward the 5nm node.
In order to further understand the processing sensitivities of the EUV resist process, TEL and imec have continued their
collaborative efforts. For this work, TEL has delivered and installed the state of the art, CLEAN TRACK™ LITHIUS
Pro™ -EUV coater/developer to the newly expanded imec 300mm cleanroom in Leuven, Belgium. The exposures
detailed in this investigation were performed off-line to the ASML EUV Alpha Demo Tool (ADT) as well as on the inline
ADT cluster with CLEAN TRACK™ ACT™ 12 coater/developer. As EUV feature sizes are reduced, is it apparent
that there is a need for more precise processing control, as can be demonstrated in the LITHIUS Pro™ -EUV. In
previous work from this collaboration1, initial investigations from the ACT™ 12 work showed reasonable results;
however, certainly hardware and processing improvements are necessary for manufacturing quality processing
performance. This work continues the investigation into CDU and defectivity performance, as well as improvements to
the process with novel techniques such as advanced defect reduction (ADR), pattern collapse mitigation with FIRM™Extreme and resolution improvement with tetrabutylammoniumhydroxide (TBAH).
The reduction of line width roughness (LWR) is a critical issue in developing resist materials for EUV lithography and
LWR represents a trade-off between sensitivity and resolution. Additional post pattern processing is expected as an LWR
reduction technique without impact to resolution or sensitivity. This paper reports the LWR reducing effect of a post-development
resist-smoothing process. Approximately 20% improvement in LWR for ArF immersion exposed resist patterns was achieved for two types of resist and two illumination conditions. The LWR after BARC etching in which
resist-smoothing was applied was decreased relative to the case in which smoothing was not applied. Resist-smoothing
process also reduced LWR of an EUV exposure resist pattern by approximately 10%. These results confirm that resistsmoothing
process is robust for different resists and illumination conditions.
This paper summarizes the development of EUV resists at Semiconductor Leading Edge Technologies (Selete): the
benchmarking results of more than 160 EUV resists from resist manufacturers using the small field exposure tool
(SFET) and the selection of the Selete standard resists (SSR) for the SFET. We discuss the current status of EUV
resist performance compared to the targets for 32-nm half-pitches (hp) concerning resist sensitivity, ultimate
resolution, and line-width-roughness (LWR). In addition we show the screening results of new resin materials.
One of the biggest issues in extreme ultraviolet (EUV) lithography technology is resist material development to
improve optimum exposure dose and reduce line edge roughness (LER)/ line width roughness (LWR) and resolution. In
order to attain these development targets, various kinds of challenges and innovative ideas are addressed by resist
material researchers, for instance, introduction of polymer with lower molecular weight and increase of photo acid
generator (PAG) addition amount have been presented. It is expected that these changes of resist materials will have big
influence on not only general lithography performance but also track performance.
In this paper, the application performance of EUV photoresist material, especially the spread behavior of photoresist
just after resist dispense for a coating process, is evaluated using the model resist, dynamic contact angle measurement of
resist material, dynamic drop base diameter measurement of resist droplet and so on. We have found that resist materials
with small polymer size and high PAG loading have low spread property. From these results, we propose a new
hypothesis that localized distribution of solid components that is formed just after resist dispense remains in a resist film
after pre-baking and impacts resist performance.
In extreme ultraviolet (EUV) lithography, exposures are and can only be performed in vacuum (<1x10<sup>-5</sup> Pa). At
present though, conventional resist processing technologies before and after exposure (coating, post application bake,
post exposure bake, etc.) are performed in atmospheric pressures. Investigations on the possibility of a
EUV-specialized resist processing system; specifically, the development of a 300mm wafer compatible, vacuum-based
resist baking and cooling system is presented. Comparative evaluations with conventional atmospheric-based systems
were made from the viewpoint of resist lithographic performance (sensitivity, resolution, line width roughness) and
resist outgassing rate. As a result, an improvement in LWR was also observed in vacuum post application bake and
post exposure bake. However, a difference in resist lithographic performance depending on the type of resist material
used was observed between resist processes performed in-atmosphere and in-vacuum. Lastly, the vacuum based bake
process was found to have no significant effect on resist outgassing rate released.
The measurement 'lower limit' and repeatability of EUV resist outgassing analysis using the pressure rise and gas
chromatography mass spectrometry (GC-MS) methods are investigated and discussed. Resist outgassing rate and amount
measurement results showed a good repeatability with the application of the same method. As for measurement
differences between dissimilar analysis methods (pressure rise and GC-MS), a relative difference of around 10 times was
obtained. In addition, qualitative analysis performed using the GC-MS showed the need for clean measurement
environment (significantly high vacuum conditions) to reduce the effect of background components affecting the
measurement quality. Under such measurement conditions, an accurate analysis of the exact source of resist outgassing
components was identified. As a result, it was confirmed that resist outgassing of the EUV resist is mostly composed of
photo acid generator and protecting group byproducts.
The main challenge facing the implementation of EUV resist and processing has been concurrent achievement of high
sensitivity, high resolution, and low line width roughness (LWR). In order to improve the performance of EUV resist,
Selete is actively pursuing its benchmarking. The results from this benchmarking were found to be as follows: E<sub>size</sub>
improved with the increasing capability of EUV pattern exposure. Sensitivity improved during this year. Resolution is
found to be almost sufficient for 32-nm half-pitch (hp), but not quite good enough for 22-nm hp. Resist blur of the resist,
which marked good score in benchmarking, is found to be 10nm to 11nm. LWR is still far from its target value.
Extreme ultraviolet (EUV) resist outgassing is viewed as one of the main factors to be considered in the research and development of EUV resists. The release of resist by outgassing in a high-vacuum EUV exposure tool system can mean contaminated optics which in effect causes a decrease in EUV energy reaching the wafer surface. An energy decrease could translate to lower throughputs and lesser productivity. In this paper, the quantification of resist outgassing upon EUV exposure is discussed. Special attention is given to the variation of resist outgassing quantification between evaluation tools of different beam intensities using the pressure rise method. Besides the commonly used resist outgassing rate calculation, the utilization of the resist outgassing amount as basis for comparison is proposed. Three types of resists were analyzed in two resist outgassing evaluation tools of different EUV beam intensities. As a result, resist outgassing rate was found to vary 19 to 109 times between evaluation tools. In contrast, resist outgassing amount was found to vary 1 to 2 times between evaluation tools. From these results, it is proposed that resist outgassing evaluations be performed using resist outgassing amount.
The main development issue regarding EUV resist has been how to concurrently achieve high sensitivity, high resolution, and low line width roughness (LWR). This paper describes the current status of EUV resist development at Selete with a small field exposure tool (SFET). Selete standard resist 2 (SSR2) can simultaneously resolve 26-nm dense and isolated lines with the SFET. Our top data for resolution with annular illumination shows a 25-nm half-pitch. In evaluating resist performance, resist blur should be estimated separately from exposure tool fluctuations. By considering the aberration, flare, and actual illumination shape, resist blur can be estimated more accurately. We estimate the resist blur for SSR2 to be between 9.5 and 10.4 nm as sigma of the Gaussian convolution. We also present benchmarking results for suppliers' samples. Though sensitivity has been improved somewhat in some resists, further improvement is necessary. Further reduction of LWR is especially needed.
To keep in pace with the highly accelerated speed of development of EUV resists, the use of the pressure rise method in the screening of EUV resist outgassing was utilized. This method was used for its advantage of in-situ applicability and evaluation speed (short evaluation time). Both “outgassing rate” [molecules/cm2/s] and “outgassing amount” [molecules/cm2] unit conventions have been obtained. In the conference, an overview of the latest EUV resist outgassing analysis results using various EUV resists (i.e. chemical amplified, PHS, acrelate, high Ea, low Ea, negative-tone, molecular, etc.) will be discussed in detail.
Surface roughness of molecular and polymer resists were probed with an atomic force microscope (AFM) and analyzed
using the power spectrum density (PSD) function. The PSD curve obtained from AFM image of the molecular resist
showed a broad profile dependent on the exposure dose and small roughness. The PSD increased more in the low spatial
frequency range after the exposure and the correlation length was increased. Meanwhile, the PSD of the polymer resist
showed a narrow profile with respect to the dose and large roughness. Overall increase in PSD with respect to the spatial
frequency was observed after the exposure.
In photomask manufacturing, the corner and the edge of the photomask are stained by photo-resist after coating. Since such resist remains cause the particles when substrates are transferred inside the photomask manufacturing equipment, it is important to remove the stained areas. The scanning type photomask edge resist remover developed this time enables a rapid and accurate resist removal compared with similar type tool. Besides, the edge remover reduces the process time of edge resist removal to set slightly narrowing the removal width. The removal speed varies according to removal conditions; it decreases when the resist film density is high such as after the pre-bake. When determining removal conditions, defect and linearity of resist removal line should be well considered as well as the removal speed. It is important to define a balance among the thinner dispense rate, N2 flow and exhaust pressure to prevent defects and optimize the arm velocity to obtain good linearity of resist removal line. With this new edge resist remover, it is also possible to make a complex removal line that is difficult by conventional technology.
The coating procedure of polymer solutions by the scanning technique is developed for LSI technologies at the next generation, where a polymer solution as resists and inter-layer dielectric films is coated on a flat substrate, and then only the solvent is vaporized and removed, and finally the thin film is remaining there. In case of applying to the photo-lithography process, scan coating and its drying processes work together for astonishing flatness in 1% fluctuation range. When the coated polymer solution is dried under reduced pressure or vacuum, the thickness distribution of the resultant film should be accurately prospected and controlled by parameters. The film thickness is generally thicker at the edge and thinner inside from there than the average thickness. A typical thickness profile of a resist film is shown in Figure 1 . The phenomena are always observed, but have not been analyzed numerically. In this paper, we report a numerical model of the drying process of liquid film including polymers and give the essential parameters to the coating and drying processes. The parameters are focused on a vaporization rate, diffusion coefficients, coated solution thickness and intrinsic viscosity, which were calculated by simplified dynamical models of Langmuir's vaporization rate equation and Einstein relation at complex polymer solutions.