In recent years, 193nm immersion lithography has been extended instead of adopting EUV lithography. And multi-patterning technology is now widely applied, which requires tighter specification as the pattern size gets smaller on advanced semiconductor devices. Regarding the mask registration metrology, it is necessary to consider some difficult challenges like tight repeatability and complex In-Die pattern measurement. In this study, the registration measurement capability was investigated on new registration metrology tool IPRO5+, and new measurement method called Model-Based measurement was evaluated. And the performance and the prospect for advanced technology masks of the IPRO5+ were discussed based on the evaluation results.
193nm immersion lithography is the mainstream production technology for the 20nm and 14nm logic nodes.
Considering multi-patterning as the technology to solve the very low k1 situation in the resolution equation puts
extreme pressure on the intra-field overlay, to which mask registration error is a major error contributor. The
International Technology Roadmap for Semiconductors (ITRS) requests a registration error below 4 nm for each
mask of a multi-patterning set forming one layer on the wafer. For mask metrology at the 20nm and 14nm logic
nodes, maintaining a precision-to-tolerance (P/T) ratio below 0.25 will be very challenging. Mask registration error
impacts intra-field wafer overlay directly and has a major impact on wafer yield. We will discuss a solution to
support full in-die registration metrology on reticles.
With the shrinking of devices, aggressive OPC is becoming imperative. Generally, OPC must be kept within photomask
manufacturing limits, but at process and OPC development stages, patterns exceeding photomask manufacturing and
inspection limits are often included. To resolve this issue, MRC (Mask Rule Checking) is executed as a method to verify
patterns exceeding photomask manufacturing and inspection limits. Two options are available in MRC to solve errors:
(1) repair layout (or OPC) of corresponding areas; or (2) manufacture photomask including corresponding areas but with
no inspection. Option (1) is generally extremely time-consuming, and if lithographically feasible, (2) would be selected.
However, if detected error flags become massive, it is nearly beyond human control to take care of configurations of
DNIR(Do Not Inspect Region). In addition, massive amounts of DNIR will augment inspection tool setup time almost
factorial. Further, inspection tools have limitations in DNIR setup method, and DNIR settings that do not meet criteria
will be considered as setting violations. Therefore, we developed TLDD (Toppan Layout Driven DNIRs), a tool that
automatically generates DNIR based on detected by MRC. This tool has the following features: (1) applies limitations to
the number of DNIRs; (2) follows DNIR limitations of inspection tools; and (3) follows both (1) and (2) upon which
DNIR area is minimized as much as possible. By utilizing this tool, difficult-to-inspect regions can be automatically set
as DNIR independent of DNIR rules of inspection tools or individual operator skills, while enabling inspection of
important areas at high sensitivity.
Technical demand for the photomask is becoming severer along with super-miniaturization of the semiconductor
patterns as shown in the ITRS roadmap. Defect inspection is especially becoming more challenging and difficult as the
photomask design rules continue to shrink toward hp65-45nm and below. One of the factors for such difficulties is
aggressive OPC (Optical Proximity Correction), which makes defect inspection extremely difficult. In lithography, ArF
immersion lithography will be predominantly used as one of the powerful candidates for the technology for hp65-45nm.
Therefore, we have to assure zero printable defects assuming the use of ArF immersion lithography. Recently, there is
another issue of increase in mask production cost, causing QCD balance to start to collapse. To cope with this new
problem, tool operation is being considered for inspections ranging from accelerating inspection in R&D phase to
reasonable inspection in production phase. In this paper, inspection concept for operation of inspection tools in R&D
and production phases is discussed, with special focus on the aerial image based inspection.
We examined two EPL mask fabrication processes to control precisely image placement (IP) on the EPL masks. One is a wafer process using an electrostatic chuck during an e-beam write and another is a membrane process using a mechanical chuck during the e-beam write. In the wafer process, the global IP is corrected during the e-beam write on the basis of the IP data taken with x-y metrology tool. In the membrane process, the global IP is corrected during the e-beam write on the basis of the data taken with the x-y metrology tool and taken in situ with the e-beam writer. The resist and final global IP (3s) of the wafer process is 7.2 nm and 10.6 nm. For the average local IP errors (3s), the local IP of 5.7 nm at the resist step increases to 14.7 nm at the final step due to process-induced distortions. The local IP could be reduced to 6.0 nm by applying the constant scale value to the mask process. In the membrane process, the resist and final global IP (3s) is 15.3 nm and 17.1 nm. With more detectable alignment marks, it would be possible to improve the global IP. For the average local IP errors (3s) of the membrane process, the average resist and final local IP are 6.7 and 7.1 nm which shows no PID. The two approaches proved to control IP more accurately than the conventional one.
The process of inspection and repair for LEEPL masks is increasingly required. A stencil mask inspection system EBScanner (Tokyo Seimitsu), using transmission electron beam, was investigated defect inspection capability on LEEPL masks. We fabricated a defect standard mask (DSM) in which programmed defects were formed, to estimate the performance of the inspection system. We performed experiments on printability of the DSM and Area MEEF (Mask Error Enhancement Factor) of LEEPL. As a result, correlation between area of pattern on mask and that on wafer is excellent, and Area MEEF is 1.19. The killer defect was defined based on the printing result on wafer. The defect size is measured by pattern shape analysis tool MaskEXPRESS (Toppan Printing). We checked the detection rate of killer defects and the number of false or real defects other than programmed defects by optimizing sensitivity of EBScanner. In case that a lot of false defect and very small defect (not crucial) are detected due to the non-uniformity of the pattern size, it takes too much time for defect review and practical classification. For reducing this work, we studied some solutions. And thus, we will discuss the analysis of EBScanner’s inspection image, including the defect classification.