We specifically studied the influence of a setback-layer thickness on the device performances so as to optimize the required value. Theoretical analysis shows that an optimized setback-layer thickness is available to effectively reduce the barrier height while maintain good device performances. In this work, the effects of a setback-layer thickness on the DC and RF performances of an InGaP/GaAs heterojunction bipolar transistor (HBT) are investigated. Based on the theoretical analysis, the optimized setback-layer thickness WSB is about of 10~30Å for analog amplification. On the other hand, for digital saturated logic application, i.e., a small offset voltage with an acceptable current gain, the optimized WSB could be up to 50 Å. Therefore, this analysis and predication may cause the considerable promise for practical circuit applications.
An interesting InGaP/InGaAs quantum-well delta-doped-channel field-effect transistor is fabricated and demonstrated. Due to the employed InGaAs dual quantum-well delta-doped-channel structure and Schottky behaviors of InGaP "insulator," good DC properties including higher turn-on voltage, lower leakage current, better linearity, and good RF performances are obtained. In addition, the experimental results are fitted well with theoretical simulation data based on a two-dimensional simulator. Moreover, the studied device exhibits relatively negligible temperature-dependent characteristics over wide operating temperature region (300<T<450K). Therefore, the studied device provides the promise for high-temperature and high-performance microwave electronic applications.
The DC performances of a novel InP/InGaAs tunneling emitter bipolar transistor (TEBT) are studied and demonstrated. The studied device can be operated under an extremely wide collector current regime larger than 11 decades in magnitude (10-12 to 10-1A). A current gain of 3 is obtained even operated at an ultra-low collector current of 3.9x10-12A (1.56x10-7 A/cm2). The common-emitter and common-base breakdown voltages of the studied device are higher than 2 and 5V, respectively. Furthermore, a very low collector-emitter offset voltage of 40 mV is found. The temperature-dependent DC characteristics of the TEBT are measured and studied. Consequentially, based on experimental results, the studied device provides the promise for low-power electronics applications.