193nm immersion lithography, with the single-exposure resolution limitation of half-pitch 38nm, has extended its
patterning capability to about 20nm using the double-patterning technique. Despite the non-trivial sub-20nm
patterning challenges, several NAND Flash manufacturers are already pursuing for sub-16nm patterning technology.
25nm NAND flash memory has already begun production in 2010, and given the typical 2-year scaling cycle, sub-16nm
NAND devices should see pilot or mass production as early as 2014. Using novel patterning techniques such as sidewall
spacer quadruple patterning (upon 120nm to 128nm pitch using dry ArF lithography) or triple patterning (upon 90nm
pitch using immersion ArF lithography), we are able to extend optical lithography to sub-16nm half-pitch and
demonstrate the lithographic performance that can nearly meet the ITRS roadmap requirements.
In this paper, we conduct an in-depth review and demonstration of sidewall spacer quadruple patterning; including
300mm wafer level data of the mean values and CDU along with a mathematical assessment of the various data pools for
sub-16nm lines and spaces. By understanding which processes (lithography, deposition, and etch) define the critical
dimension of each data pool, we can make predictions of CDU capability for the sidewall spacer quad patterning. Our
VeritySEM4i CD SEM tool demonstrated high measurement yield during fully automated measurements, which enables
accurate lines, spaces and CDU measurements of the sub-16nm. The patterns generated from the sidewall spacer
quadruple patterning techniques are used as a hardmask to transfer sub-16nm lines and spaces patterns to underneath
amorphous silicon and silicon oxide layers, or poly silicon layer for 1X STI or poly gate applications.
Self-Aligned Double patterning (SADP) technology has been identified as the main stream patterning technique for
NAND FLASH manufacturers for 3xnm and beyond. This paper demonstrates the successful fabrication of 32nm halfpitch
electrical testable NAND FLASH wordline structures using a 3-mask flow. This 3-mask flow includes one critical
lithography step and two non-critical lithography steps. It uses a positive tone (spacer as mask) approach to create 32nm
doped poly wordlines. Electrical measurements of line resistance are performed on these doped poly wordlines to
demonstrate the capability of this patterning technique. Detailed results and critical process considerations, including
lithography, deposition and etch, will be discussed in this paper.
Sidewall Spacer Double Patterning (SSDP) has been adopted for the primary patterning technique for 3x nm technology
node and beyond in flash memory device manufacturing. Three mask flow are used in SSDP process scheme in order to
form the actual device layer; Core mask to define the template pattern, Trim mask to cut (cropping) the unneeded line
ends from sidewall spacer, and Pad mask to pattern the periphery structures. Inter-layer and intra-layers alignment with
sidewall spacer double patterning requires some engineering efforts compared to traditional single patterning alignment
techniques. In this paper, we study the impacts of hard-mask materials on the inter-layer alignment as well as the mark
design and process flow impact on intra-layer alignment. For intra-layer alignment, we searched various ASML
ATHENA alignment marks and found the only workable mark (VSPM-AA157 Polar). Although the wafer quality
scores during alignment were less than 0.1% in many cases, the alignment was successful and yielded acceptable
performance for research and development activities requiring less than 10nm misalignment. Further new mark design
and test should be carried in implementing in sidewall spacer double patterning process.