As 3D NAND devices increase memory density by adding layers, scaling and increasing bits-per-cell, new overlay (OVL) metrology challenges arise. On product overlay (OPO) may decrease for critical thick layers such as thick deck-to-deck alignment, whereas high aspect ratio (Z-axis) structures introduce stress, tilt and deformation that require accurate and robust OVL measurements. Advanced imaging metrology (AIM®) targets, that consist of two side-byside periodic gratings in the previous and current layers, are typically used to measure OVL with Imaging Based Overlay (IBO) metrology systems. In this paper, we present a new approach that utilizes the Talbot effect in AIM to produce multiple contrast planes along the Z-axis, which enables a common focus position for both layers at a similar focus plane, resulting in improved measurement robustness. We will present Talbot effect theory, target design steps by metrology target design (MTD) simulator, actual measurement results on an advanced 3D NAND device and conclusions for such targets.
On product overlay (OPO) challenges continue to be yield limiters for most advanced technology nodes, requiring new and innovative metrology solutions. In this paper we will cover an approach to boost accuracy and robustness to process variation in imaging-based overlay (IBO) metrology by leveraging optimized measurement conditions per alignment layer. Results apply to both DUV and EUV lithography for advanced Logic, DRAM, 3D NAND and emerging memory devices. Such an approach fuses multi-signal information including Color Per Layer (CPL) and focus per layer. This approach with supporting algorithms strives to identify and address sources of measurement inaccuracy to enable tight OPO, improve accuracy stability and reduce overlay (OVL) residual error within the wafer and across lots. In this paper, we will present a theoretical overview, supporting simulations and measured data for multiple technology segments. Lastly, a discussion about next steps and future development will take place.
On Product Overlay (OPO) control is a critical factor in advanced semiconductor manufacturing. As feature sizes become smaller, OPO budgets become tighter, leaving less room for overlay (OVL) measurement inaccuracy. Over the last few years, overlay metrology’s focus has shifted inwards, towards accurate measurement conditions, as we aim to capture ever-smaller process and scanner variations. One method used to break down the OPO error budget is combining one or more accuracy flags and correlating them to various process impacts. Analyzing the overlay accuracy signature generated by accuracy flags can be useful for data validation, inspection and correlation to different processes and metrologies. In this paper, an extensive OVL accuracy experiment demonstrates the use of this new method. First, the method is applied to several wafers designed with intentional process variation, including variations in etch duration, Chemical Mechanical Polishing (CMP) duration, amorphous silicon (a-Si) thickness and titanium nitride (TiN) thickness. OVL results from the experimental wafers are compared with results from the reference (nominal) wafer.
In the latest 3D NAND devices there is a larger focus on measurement accuracy control, coupled with more traditional minimization of Total Measurement Uncertainty (TMU). Measurement inaccuracy consumes an increasingly significant part of the overlay (OVL) budget, requiring control and optimization.
In this paper we will show the improvement in imaging OVL measurement accuracy using wave tuning (WT) capability combined with advanced algorithms to address 3D NAND process challenges. In addition to new OVL target designs that take advantage of WT capability, we also demonstrate improvement in OVL model residuals through optimization of measurement bandwidth, focus position and number of grab frames. Improvements in precision and tool-to-tool matching are also realized through both optimization of the region of interest (ROI) and splitting measurement areas using a dual-recipe technique.
Tool induced shift (TIS) is a measurement error attributed to tool asymmetry issues and is commonly used to measure the accuracy of metrology tools. Overlay (OVL) measurement inaccuracy is commonly caused by lens aberration, lens alignment, illumination alignment and asymmetries on the measured target. TIS impacts total measurement uncertainty (TMU) and tool-to-tool matching, and TIS variation across wafer can account for inaccuracy, if not fully corrected, as it depends on the incoming process condition. In addition, both lot-to-lot and wafer-to-wafer process variation are influenced by TIS in terms of overlay performance, which also includes metrology tool-to-tool efficiency in terms of throughput. In the past, TIS correction was only done using a small sampling, resulting in additional error in the measurement which was not corrected. Hence, a new methodology is explored to improve overlay measurement accuracy by Modeled-TIS (M-TIS). This paper discusses a new approach of harnessing Machine Learning (ML) algorithms to predict TIS correction on imaging-based overlay (IBO) measurements at the after-develop inspection (ADI) step. KLA’s ML algorithm is trained to detect TIS error contributors to overlay measurements by training a model to find the required TIS correction for one wafer. This information, along with additional accuracy metrics, is then used to predict the TIS for other wafers, without having to actually measure the wafers. In this paper, we present the results of a case study focusing on DRAM and 3D NAND production lots.
As the semiconductor industry rapidly approaches the 3nm lithography node, on product overlay (OPO) requirements have become tighter and as a result, residuals magnitude requirements have become even more challenging. Metrology performance enhancements are required to meet these demands. Color Per Layer (CPL) is a unique imaging overlay metrology approach that enables the measurement of each layer with individually-optimized wavelength and focus position. CPL allows the user to custom-define the most suitable conditions per layer, thereby ensuring optimal performance. Imaging-based overlay (IBO) utilizes CPL in order to overcome inaccuracies due to interactions between bottom and top layers. These layers are fundamentally different in that the top grating is usually the photoresist layer, but the bottom grating can be any process layer. Therefore, optimizing the conditions for each layer will maximize measurement accuracy. KLA’s Archer™ 700 metrology tool addresses these metrology challenges by putting CPL to use, where the Wave Tuner (WT) allows the user to select a specific wavelength. This paper presents this novel CPL approach and discusses its reduction in OPO and contrast, and reviews use cases from DRAM and 3D NAND. We will present the results from these case studies, focusing on SK Hynix DRAM production wafers.