EUV lithography (EUVL) is the most promising solution for 16nm HP node semiconductor device manufacturing and
beyond. The fabrication of defect free EUV mask is one of the most challenging roadblocks to insert EUVL into high
volume manufacturing (HVM). To fabricate and assure the defect free EUV masks, electron beam inspection (EBI) tool
will be likely the necessary tool since optical mask inspection systems using 193nm and 199nm light are reaching a
practical resolution limit around 16nm HP node EUV mask. For production use of EBI, several challenges and potential
issues are expected. Firstly, required defect detection sensitivity is quite high. According to ITRS roadmap updated in
2011, the smallest defect size needed to detect is about 18nm for 15nm NAND Flash HP node EUV mask. Secondly,
small pixel size is likely required to obtain the high sensitivity. Thus, it might damage Ru capped Mo/Si multilayer due
to accumulated high density electron beam bombardments. It also has potential of elevation of nuisance defects and
reduction of throughput. These challenges must be solved before inserting EBI system into EUV mask HVM line.
In this paper, we share our initial inspection results for 16nm HP node EUV mask (64nm HP absorber pattern on the
EUV mask) using an EBI system eXplore® 5400 developed by Hermes Microvision, Inc. (HMI). In particularly, defect
detection sensitivity, inspectability and damage to EUV mask were assessed. As conclusions, we found that the EBI
system has capability to capture 16nm defects on 64nm absorber pattern EUV mask, satisfying the sensitivity
requirement of 15nm NAND Flash HP node EUV mask. Furthermore, we confirmed there is no significant damage to
susceptible Ru capped Mo/Si multilayer. We also identified that low throughput and high nuisance defect rate are critical
challenges needed to address for the 16nm HP node EUV mask inspection. The high nuisance defect rate could be
generated by poor LWR and stitching errors during EB writing of 64nm HP resist pattern. This result suggests we need
further improvements not only in the EBI inspection system but also the patterning processes for 16nm HP node EUV
The new generations of photomasks are seen to bring more and more challenges to the mask manufacturer. Maskshops
face two conflicting requirements, namely improving pattern fidelity and reducing or at least maintaining acceptable
writing time. These requirements are getting more and more challenging since pattern size continuously shrinks and data
volumes continuously grows.
Although the classical dose modulation Proximity Effect Correction is able to provide sufficient process control to the
mainstream products, an increased number of published and wafer data show that the mask process is becoming a nonnegligible
contributor to the 28nm technology yield. We will show in this paper that a novel approach of mask proximity
effect correction is able to meet the dual challenge of the new generation of masks.
Unlike the classical approach, the technique presented in this paper is based on a concurrent optimization of the dose and
geometry of the fractured shots. Adding one more parameter allows providing the best possible compromise between
accuracy and writing time since energy latitude can be taken into account as well. This solution is implemented in the
Inscale software package from Aselta Nanographics.
We have assessed the capability of this technology on several levels of a 28nm technology. On this set, the writing time
has been reduced up to 25% without sacrificing the accuracy which at the same time has been improved significantly
compared to the existing process. The experiments presented in the paper confirm that a versatile proximity effect
correction strategy, combining dose and geometry modulation helps the users to tradeoff between resolution/accuracy
and e-beam write time.
We are evaluating the resolution capability of character projection (CP) exposure method using a Multi Colum Cell
Proof of Concept (MCC-POC) tool. Resolving of 14nm half pitch (HP) 1:1 line and space (LS) patterns are confirmed
with fine openings of a DNP fabricated CP mask for 10:1
de-magnification ratio. CP exposure has been proven to exhibit
high resolution capabilities even under the most challenging optimization conditions that are required for throughput
enhancement. As a result of evaluating the resolution capability of CP technology, it became apparent that the CP
technology has strong potentials to meet future challenges in two areas. One is where an increased number of CP with
variable illumination technology gives a higher throughput which has been the main objective behind the development of
this technology, and the other is to achieve higher resolution capability that is one of the strengths of CP exposure
method. We also evaluated the resolution on Quartz mask blanks instead of Si wafers and obtained 18nm HP 1:1
resolution with CP exposure.
The load of VSB-EB mask writers has significantly increased since particularly RET/OPC and CMP dummy pattern
generation technologies were widely adopted into designs at advanced nodes, with the result that the volume of mask
data patterns was increased exponentially. In order to reduce the load of VSB mask writer, we've focused on CMP
dummy patterns and developed a method of reducing CMP dummy pattern, which can smartly write CMP dummy
patterns without not only deteriorating the CMP effects by them and also increasing the total number of the mask
writer's shot count. To that end, we are aiming to establish a
VSB-mask-writer-friendly CMP dummy pattern generation
flow with CMP simulator developers by providing a mask writer parameter for them.
This paper shows the first experimental results of our mask writer's load reduction work.
We have evaluated a unified mask pattern data format named "OASIS.MASK"1 and a unified job deck format
named "MALY"2 for mask tools as the input data formats of the inspection tool using the mask data and the photomask
produced with the 65nm design rule. The data conversion time and the data volume for the inspection data files were
evaluated by comparing with the results for using the native EB data and the native job deck data. The inspection speed
and the defect number of the inspection tool were also evaluated with the actual inspection tool. We have confirmed that
there is no large issue in applying OASIS.MASK and MALY to the input data formats of the inspection tool and they
can become the common intermediate format in our MDP flow. The detail of evaluation results will be mainly
introduced in this paper.
The design shrinking of semiconductor devices and the pattern complexity generated after OPC (optical proximity
correction) have an impact on the two major cost consuming processes in mask manufacturing, EB (electron beam)
writing and defect assurance. Mask-DFM (design for manufacturing) is a technique with various steps ranging from
the design to the mask manufacturing to produce the mask friendly designs and to reduce the workload in the advanced
mask production. We have previously reported on our system, called MiLE (Mask manufacturing Load Estimation),
which quantifies the mask manufacturing workload by using the results of mask layout analyses. MiLE illustrates the
benefits of mask-DFM efforts as numerical indexes and accelerates the DFM approaches. In this paper, we will show
the accuracy of the workload estimation of the advanced devices by the comparison between the indexes and the process
times in the actual mask manufacturing. The throughput of MiLE calculation of the production masks of a 65nm device
As the pattern feature sizes become smaller, photomask assurance by one-dimensional criteria using a CD-SEM is reaching its limits. For instance, minute steps generated by OPC (Optical Proximity Correction), especially under the influence of corner rounding, are hard to measure. Thus, photomask assurance by means of two-dimensional features has been studied.
Conventionally, in simulations to predict the printed shape on the wafer, OPCed data pattern have been used. While the OPCed data pattern represents the ideal pattern fidelity, actual pattern on a real photomask is different from the ideal shape. In addition, the increase of MEEF (Mask Error Enhancement Factor), along with the fine-than-ever pattern feature size, emphasizes the difference between the simulation result and the actually printed result on the wafer. To realize the two-dimensional assurance, we have to think of a method to predict the wafer image accurately. This is also important when we have to verify and manage the lithographic hotspots.
For this purpose, we have been studying a mask model, a technique to take into consideration the actual pattern fidelity on the photomask, by modeling mask patterns' linearity, proximity, corner-rounding, etc., for each mask making process. By applying the mask model to OPCed design pattern, mask pattern shapes were found to be accurately predicted before mask making.
Furthermore, we studied hotspot verification flow using the mask model. By the application of the mask model on the data pattern for the optical simulation, we accurately predicted the shape printed on the wafer, and accurately verify hotspots. This is expected to lead to assurance of photomask using two-dimensional shape.
In the continuous battle to improve critical dimension (CD) uniformity, especially for 45-nanometer (nm) logic
advanced products, one important recent advance is the ability to accurately predict the mask CD uniformity
contribution to the overall global wafer CD error budget. In most wafer process simulation models, mask error
contribution is embedded in the optical and/or resist models. We have separated the mask effects, however, by
creating a short-range mask process model (MPM) for each unique mask process and a long-range CD
uniformity mask bias map (MBM) for each individual mask. By establishing a mask bias map, we are able to
incorporate the mask CD uniformity signature into our modelling simulations and measure the effects on global
wafer CD uniformity and hotspots. We also have examined several ways of proving the efficiency of this
approach, including the analysis of OPC hot spot signatures with and without the mask bias map (see Figure 1)
and by comparing the precision of the model contour prediction to wafer SEM images. In this paper we will
show the different steps of mask bias map generation and use for advanced 45nm logic node layers, along with
the current results of this new dynamic application to improve hot spot verification through Brion Technologies'
model-based mask verification loop.
ADAS (Automated Defect Analysis Software) is the first product to fully automate mask defect analysis for mask shops
and fabs. ADAS classifies and dispositions photomask defects quickly and accurately. Disposition is based on defect
size and printability measurements from simulation.
Full analysis of inspection reports with 100 defects requires 2 seconds. Printability measurements match AIMS within 6
percent at 3 sigma on 45 nm test masks. Repeatability is 5 percent at 3 sigma over multiple inspections. ADAS can
reduce the need for production AIMS measurements by 90% and eliminate operator review errors and the repelliclizations
they cause. ADAS increases overall inspection efficiency for mask shop first-inspection and final
inspection. It can automate fab requalification inspections and eliminate the need for incoming inspection.
One of the most critical points for accurate OPC is to have accurate models that properly simulate the full process from
the mask fractured data to the etched remaining structures on the wafer. In advanced technology nodes, the CD error
budget becomes so tight that it is becoming critical to improve modeling accuracy. Current technology models used for
OPC generation and verification are mostly composed of an optical model, a resist model and sometimes an etch model.
The mask contribution is nominally accounted for in the optical and resist portions of these models. Mask processing
has become ever more complex throughout the years so properly modeling this portion of the process has the potential
to improve the overall modeling accuracy. Also, measuring and tracking individual mask parameters such as CD bias
can potentially improve wafer yields by detecting hotspots caused by individual mask characteristics. In this paper, we
will show results of a new approach that incorporates mask process modeling. We will also show results of testing a
new dynamic mask bias application used during OPC verification.
Load of photomask manufacturing for the most advanced semiconductor devices is increasing due to the complexity of
mask layouts caused by highly accurate RET or OPC, tight specification for 2D/3D mask structures, and requirements of
quick deliveries. The mask cost becomes a concern of mask users especially in SoC businesses because the number of
masks required throughout the wafer process is almost the same for each product regardless of the variety in production
volume when a unified platform is applied to the designs. Shares of mask cost within total production cost cannot be
ignored especially in small volume SoC products.
DFM (design for manufacturing) is inevitable in a mask level as well as in a wafer level to solve the cost problem.
"Mask-DFM" is a method to decrease the burden of mask manufacturing and to improve the yield and quality of masks,
not only by modification of mask pattern layouts (design) but also all other things including utilization of designer's
We have developed our Mask-DFM system called "MiLE", that calculates mask-manufacturing workload through
layout analyses combining information of mask configuration, and visualizes the consequence of Mask-DFM efforts.
"MiLE (Mask manufacturIng Load Estimation)" calculates a relative index which represents the mask manufacturing
workload determined by factors of 1) EB writing, 2) defect inspection/repair, 3) materials and processes and 4)
specification. All the factors are computed before tape-outs for mask making in the system by the following methods.
To estimate EB writing time, we applied high-throughput simulator and counted the number of "shot", minimum figure
unit in EB writing, by using post-OPC layout data. Mask layout that caused troubles and extra load in mask
inspection or repair was specified from MRC (mask rule checking) of the same post-OPC data. Additional layout
analysis perceives designer's intents that are described in the layout data and these are reflected in the calculation of the
"MiLE" index. Finally, chip arrangement on a mask is retrieved from so-called electronic mask spec sheets to construct mask layouts.
"MiLE" notifies to designers the index of mask manufacturing workload that is caused by mask layout, while modification and adjustments of design or OPC are iterated to maximize device productivity in early design phases. Therefore, designers can judge and control the mask manufacturability, or mask cost by designs and additional intents
useful for mask making. In the production phases, our system releases useful information for mask manufacturing to a mask shop and decreases the mask manufacturing workload. In this paper, we report the outline and functions of MiLE system and the results of mask manufacturing workload calculation using post-OPC layout data.
Recently, mask design has been becoming more complex with the increase of data volume. Therefore, it requires more
functionality and portability in the mask specification and layout definition for the efficient data handling together with
industry standard. SEMI-P10 order format has universal layout definition for the all sorts of mask specifications. We
expect OASISTM (Open Artwork System Interchange Standard; SEMI standard P39) instead of conventional GDS-II to
come into wide use as a more compressive stream format for 45nm node and beyond. The OASIS format is suitable for
the enormous pattern file size and sub-nanometer design grid.
Although SEMI-P10 is convenient to achieve all of our requirements, its complete definition is very complicated and is
difficult to set up full parameters in the primary stage of mask design for production chips. In this work, we focused on
minimum syntax of the chip location information from portion of SEMI-P10. And we define P10-JOBDECK as a subset
of whole SEMI-P10 regulations. So, by use of P10-JOBDECK and OASIS data format, we have built up the new data
handling infrastructure such as data file transfer and pattern layout viewing for the high-end mask manufacturing.
In this system, the coordinates of P10-JOBDECK are described in 4X image with mirror inversion and tone reversal
parameters. We use 1X coordinates in P10-JOBDECK for the pattern data files because they are the dimensions familiar
to the designer, and the transformation for the mask shop is handled automatically. This style is effective for shortening
the data conversion time and preventing mishandling of data. We also developed the additional viewer functions of
HOTSCOPE® to confirm the pattern layout on the digital display.
It is possible to add mask DFM information (design information for mask manufacturability) by the extension to the full
SEMI-P10 syntax and by the use of built-in OASIS properties in the future.
In this paper, we will discuss the practical application of P10-JOBDECK and the performance results of HOTSCOPE.
Photomask pattern writer requires high-speed data processing that is conducted concurrently with the variable shaped
beam (VSB) writing. As input electron beam (EB) mask data, trapezoid data format is generally used for EB writing
because of the easier handling than polygon data format. Recent years, volume of photomask pattern data is growing
as the increase of pattern density that is caused by additional various subsidiary patterns of optical proximity correction
(OPC). OPC in design rules of 65nm and below is getting approximately 1.5 times more complex than that in the
former generation, which increases the photomask pattern data volume approximately 3 times larger.
VSB writing time is accurately estimated by counting the total number of "shots" which are primitive figures
generated in the data processing of EB writer from the trapezoid patterns in EB mask data. However, no feedback and
layout modification can be taken to LSI designs and OPC, even though problems regarding mask manufacturability such
as explosion of EB writing time is recognized after starting EB writing process.
We developed a simulator that estimates the number of "shots" in VSB EB writing by original shot division method
using design data GDSII instead of EB mask data. This simulator outputs total counts and density map of shots of EB
writing in photomask layout as well as chip layout in a short time using multi-processing. We can use this software as
a core function in our Mask-DFM solutions offering to LSI designers and CAD engineers in order to estimate mask
manufacturability before they finish mask data tape-out, and this work can reduce cost and improve TAT in mask manufacturing.
Over the last 5 years, Japanese consortium, Semiconductor Leading Edge Technologies Inc. (Selete), lead the way in developing unified mask data format. Specification of the format was released as OASIS.VSB and registered to SEMI standard, P44. It is expected that using OASIS.VSB would reduce TAT and improve efficient usage of data infrastructure. OASIS.VSB has advantages for mask data preparation since OASIS.VSB is based on OASISTM (SEMI P39) and OASIS compliant software is already commercially available. Although fundamental evaluation of OASIS.VSB have been made by Selete on technical feasibility with VSB mask writers, its performance and advantage of data handling improvement is still controversial. We have been evaluating OASIS.VSB in order to estimate the impact of data handling improvement at mask manufacturer. Figure 1 shows that OASIS.VSB has good compression ratio compared to certain VSB mask data format. Although compression ratio partly depends on data and conversion software, OASIS.VSB is about 0.7 times as small as VSB data format on weighted basis average. Furthermore, we have confirmed by simulation that OASIS.VSB can hardly affect shot count and writing time.
Unification of mask data format by OASIS.VSB can realize flexible mask data preparation (MDP) and reduce a cost of data storage. To achieve further TAT reduction, it is necessary to apply OASIS.VSB to not only mask writing data but other mask making processes such as die to database inspection and mask rule check (MRC).
Optical proximity correction (OPC) is an essential technology for critical dimension (CD) control in Low-k1 lithography. As technology node becomes tighter, more aggressive OPC is required. However, the number of so-called HOT-SPOTS is increasing dramatically. To apply OPC correctly and efficiently, we should consider the total optimization of the process in close connection with data processing, reticle and wafer fabrication process. Conventional one-dimensional CD measurement is no longer suitable for complicated two-dimensional (2D) patterns generated by OPC (e.g. JOG and SERIF). For quality assurance of mask pattern, a metrology of complicated 2D OPC patterns has been required. In our previous report, we proposed a lithography simulation based on edge extraction from a fine pixel SEM image of an actual photomask. This method is very effective for evaluating quality of 2D OPC mask patterns. Employing the method, we developed a system for guaranteeing 2D OPC patterns before shipping the mask to a wafer factory (Fig. 1). In PMJ2005, we presented some specifications required for an SEM, which was one of the key factors of this method. We estimated how factors such as field of image, image resolution, positioning error, and image magnification affect lithography simulation based on fine pixel SEM image. For mask pattern quality assurance of hp65, we found that the field of image of larger than 16μm square, the pixel size of less than 3nm, the positioning error of within +/- 1μm and the magnification error of less than 0.3% were acceptable (Table 1). Under these conditions, wafer image can be predicted with sufficient accuracy by the simulation. And then, in BACUS2005, we reported on a new SEM that was able to satisfy these specifications. In this paper, we report some evaluation results of distortion caused by not only magnification error but also rotation and position error using actual fine pixel SEM image. We will also present our evaluation results of the errors in various pattern conditions such as Dark Field/Bright Field, Pattern density.
As patterns on photomasks are getting more complex due to RET technologies, mask rule check (MRC) has become an essential process before manufacturing photomasks. Design rule check (DRC) tools in the EDA field can be applied for MRC. However, photomask data has unique characteristics different from IC design, which causes many problems when handling photomask data in the same way as the design data.
In this paper, we introduce a novel MRC tool, SmartMRC, which has been developed by SII NanoTechnology in order to solve these problems and show the experimental results performed by DNP. We have achieved high performance of data processing by optimizing the software engine to make the best use of mask data's characteristics. The experimental results show that only a little difference has been seen in calculation time for reversed pattern data compared to non-reversed data. Furthermore, the MRC tool can deal with various types of photomask data and Jobdec in the same transparent way by reading them directly without any intermediate data conversion, which helps to reduce the overhead time. Lastly it has been proven that result OASIS files are several times smaller than GDS files.
Leading-edge photomask, to which optical proximity correction (OPC)
and dummy pattern are applied, almost always has complex patterns. Complex patterns such as "Narrow Space", "Thin Pattern", "Dummy Pattern", "Closely Face-to-Face Heads" of Posi Serifs, "Narrow Waisted Pattern" formed by a Nega Serif, "Jogs", etc. are a factor to complicate photomask manufacturing. Some the problems caused by complex patterns are increase in EB writing time, and decrease in performance of etching and cleaning process caused by Cr peeling and, above all, increase in the inspection time. Patterns whose complexity is beyond the resolution limit of inspection tool are detected as false defects. Therefore, it will greatly take time for the data investigation and re-inspection, etc. for assurance, and this causes congestion of half-finished products. To improve the process efficiency, it is necessary to locate false defects, so that the Do-Not-Inspection-Area(DNIR) or replaced with simpler patterns. In order to locate false defects, it is proposed to apply Mask Rule
Check (MRC) to mask data for EB-writing.
We evaluated the accuracy of the simulation based on mask edge extraction for mask pattern quality assurance. Edge extraction data were obtained from SEM images by use of TOPCON UR-6080 in which high resolution (pixel size of 2nm) and fine pixel SEM image (8000 x 8000 pixels) acquisition is possible. The repeatability of the edge extraction and its impact on wafer image simulation were studied for a normal 1D CD prediction and an edge placement error prediction. The reliability of the simulation was studied by comparing with actual experimental exposure results with an ArF scanner. In the normal 1D CD prediction, we successfully obtained good repeatability and reliability. In 65nm node, we can predict a wafer CD with the accuracy of less than 1 nm using the simulation based on mask edge extraction. In the edge placement error prediction mode, the simulation accuracy is ~5 nm including edge extraction repeatability and the uncertainty of lithography simulation model.
The simulation with edge extraction more accurately predicts the resist pattern at line-end in which the actual mask pattern may be varied from the mask target (CAD) than a conventional simulation in which CAD is used as a mask pattern. This result supports the view that the wafer simulation with edge extraction is useful for mask pattern quality assurance because it can consider actual mask pattern shape.
OASIS (Open Artwork System Interchange Standard) is the new stream format to replace conventional GDSII and has become a SEMI standard 2003. Also, some EDA software tools already support OASIS. OASIS can apply not only layout design field but also photomask industory. OASIS is effective to reduce data volume even if it is a fractured data, therefore it is expected to solve file size explosion problem.
From mask manufacturer's perspective, it is also necessary to consider mask layout information. In present, there are various kinds of layout information and jobdeck formats. These circumstances require complicated data handling and preparation process at the mask manufacturers. Computerized automatic process needs to be more utilized to eradicate mistakes and miscommunications at the planning department. SEMI standard P10 (Specification of Data Structures for Photomask Orders) is one of the solutions. P10 is basically intended to communicate about mask order data which include layout information.
This paper reports the result of evaluation of mask data preparation unified with two SEMI standards: P39 (OASIS) and P10. We have developed a reticle pattern viewer (HOTSCOPE) which can view photomask data with combined OASIS with P10. Figure 1 shows connection between mask data formats, which include OASIS and P10 format with our reticle pattern viewer. HOTSCOPE provides reviewing mask data as a photomask image. It will interface between device manufacturers and mask manufacturers.
We investigated the specifications of scanning electron microscope required for the lithography simulation based on the edge data extracted from an actual reticle pattern in the assurance of reticle pattern in which two-dimensional optical proximity correction is applied. Impacts of field of view, positioning error and image distortion on a lithography simulation were studied experimentally. For the reticle pattern assurance in hp90, the field of view of larger than 16 μm squares, the positioning error within +/- 1 μm and the magnification error of less than 0.3% are needed. Under these conditions, wafer image can be predicted with sufficient accuracy by the simulation.
We have developed a unified mask data format named “OASIS.VSB” for Variable-Shaped-Beam (VSB) EB writers. OASIS.VSB is the mask data format based on OASIS released as a successive format to GDSII by SEMI. We have defined restrictions on OASIS for VSB EB writers to input OASIS.VSB data directly to VSB EB writers just like the native EB data. We confirmed there was no large problem in OASIS.VSB as the unified mask data format through the evaluation results. The latest version of OASIS.VSB specification has been disclosed to the public in 2005.
Recently, photomask pattern feature have become different from LSI layout pattern feature by the OPC process and CMP DUMMY pattern insertion. And then, photomask pattern data volume is very large compared with LSI layout pattern data volume. Therefore, in the usual JOBDECK pattern viewer software, it is difficult to draw those huge pattern data smoothly and quickly.
Moreover, various proposals of RET (Resolution Enhancement Technology) are made from various companies and organizations, and it is discussed by various societies. According to the RET, mask pattern feature and structure have been more complicated than the present pattern, and mask difficulty and mask cost might be going to increase and will have great anxiety.
Photomask pattern viewer, HOTSCOPE which we developed isn't an only high speed photomask pattern viewer and analyzer, but also can superpose and observe some other mask format pattern and GDS2 format pattern by changing pattern magnification and mirror processing by itself. And HOTSCOPE is the tool which fully incorporated the function required for mask manufactures, such as a plan of a mask, preparation of JOBDECK, and the mask pattern analysis purpose.
We have developed a unified mask data format named “OASIS.NEO1” for Variable-Shaped-Beam (VSB) EB writers as enhancement of unified mask data format named “NEO2”. OASIS.NEO is a pattern data format based on OASISTM3 released as GDSII replacement by SEMI. We have developed OASIS.NEO for practical use of unified mask data formats in mask data preparation (MDP) flow. For practical use, it is necessary to input OASIS.NEO data directly to VSB EB writers just like the native EB data. So we have defined restrictions on OASIS for VSB EB writers referring the restrictions in NEO based on GDSII named “GDSII.NEO4”. In this paper we proposed the specification of OASIS.NEO.
Photomasks are currently inspected based on the standard of defect size. A shortcoming of this standard is that the type of defects which do not impact on a wafer, could be detected as impermissible defects. All of them are subject to repair works and some of them require further inspection by AIMS. This is one of the factors that are pushing down the yield and the turnaround time (TAT) of mask manufacturing. An effective way to improve this situation will be to do the repair works selectively on the defects that are predicted to inflict a functional damage on a wafer. In this report, we will propose a defect evaluation system named ADRES (Advanced Photomask Defect Repair Evaluation System), featuring a function to extract edges from a mask SEM image to be passed on to a litho-simulation. A distinctive point of our system is the use of a mask SEM image with a high resolution.
Alternating phase-shifting mask (Alt-PSM) has been often viewed as one of the most practical techniques for 100nm-and-below node lithography. Among the various mask structures of the Alt-PSMs, the 'single trench with undercut structure', which has a phase shifting trench with side- etching, has been in frequent use of 130nm-node KrF lithography. It is because this structure has good optical characteristics, and it has some advantages in productivity compared with other mask structures. However, when the 'single trench with undercut' type Alt-PSM is applied to the 100nm-and-below node ArF lithography, the narrow chrome line width restricts the undercut width and limits the lithographic performance. Therefore a new structure is required.