Advanced processing methods like multiple patterning necessitate improved intra-layer uniformity and balancing monitoring for overlay and CD. To achieve those requirements without major throughout impact, a new advanced mark for measurement is introduced. Based on an optical measurement, this mark delivers CD and overlay results for a specified layer at once. During the conducted experiments at front-end-of-line (FEOL) process area, a mark selection is done and the measurement capability of this mark design is verified. Gathered results are used to determine lithography to etch biases and intra-wafer signatures for CD and overlay. Furthermore, possible use cases like dose correction recipe creation and process signature monitoring were discussed.
Before each wafer exposure, the photo lithography scanner’s alignment system measures alignment marks to correct for placement errors and wafer deformation. To minimize throughput impact, the number of alignment measurements is limited. Usually, the wafer alignment does not correct for intrafield effects. However, after calibration of lens and reticle heating, residual heating effects remain. A set of wafers is exposed with special reticles containing many alignment marks, enabling intra-field alignment. Reticles with a dense alignment layout have been used, with different defined intra-field bias. In addition, overlay simulations are performed with dedicated higher order intra-field overlay models to compensate for wafer-to-wafer and across-wafer heating.
As device design rule has been made pattern size shrink, LELE (Litho-Etch- Litho-Etch) process is used in advance pattern process more and more. The CD control is one of the most critical factors for semiconductor manufacturing. However, the numbers of current in-line measurement points are not sufficient for the whole wafer CD monitoring. It’s the goal to increase inline monitor capacity without suffering process cycle time. To generate an innovation pattern to reach the goal is the purpose for the advance pattern process.
This paper is going to introduce the detection of CD variation by using overlay metrology in LELE process. The target mark was designed from AIM (Advanced Imaging Metrology) overlay mark. By placing Layer 1 and Layer 2 AIM pattern side by side, CD variation will cause related position changed. And it is able to be detected by overlay tool. On the other hand, overlay shift will not influence this model. It has an advantage over the conventional CD measurement tool. First, the overlay tool throughput is 5~10 times faster than traditional CDSEM and the measurement time is saved. Second, we are able to measure CD and overlay at the same time. Both CD/AA performances are considered and the throughput is also gained.
The minimum design rule of device patterns for LSI implant layers has been shrinking constantly according to the
industry requirements. Wavelength has been shortened and numerical aperture (NA) of the scanner has been enlarged to
catch up with the required shrinkage. Implant layers are unique because the resist is nearly always used without an
antireflective coating, and as a result, the resist is in direct contact with a multitude of substrate materials. In implant
applications, the wafer topography sacrifices some of the lithographic performance in order to obtain adequate features
on both top and bottom of the topography. KrF lithography has applied to most of the ion implant levels at today's
To solve the several issues in ion implant process, New KrF resist was designed specifically for the lithographic /
implantation process requirements.
As the pattern size shrinking down below 1/4 of the exposure wavelength, the NA of exposure tool has to be increased
proportionally. The use of hyper NA and immersion exposure system for improving image quality may result in a
small workable process window. Hence, resolution enhancement technology (RET) becomes a necessity for
semiconductor manufacturing. Previous studies have demonstrated many RETs, such as CPL, DDL, IML and DPT etc.
can improve the process window for different applications.1,2,3,4 In this work, we show manufacturing
implementation of a 32nm node SRAM cell with different RET approaches. The diffusion, poly, contact, and metal
layers were chosen as the target design. The process development project starts from the wafer exposure scheme
setting, which includes the multi-exposure, illumination shape and mask type. After the RET has been specified, the
process performance indexes, such as MEEF, PW, and CDU are characterized by using both simulation and empirical
The mask design and OPC is implemented After the mask data preparation step, we then optimize exposure
parameters for best printing performance and follow it by verifying actual wafer data. The mask making spec and
DFM design rule constrains have been assessed and recommended for 32nm node manufacturing. Also, we have
examined the immersion process defect impact and control methodology for production environment. In this paper,
we report the result of optimizing RET process (including mask data generation, reticle making specifications, and
wafer printing) for 32nm SRAM. With 193nm ultra high NA immersion exposure scanner (such as ASML /1900), it
is capable of meeting 32nm SRAM manufacturing requirement.
Obtaining good post-etching CD uniformity is getting more and more important in advanced processes such as 90 nm, 65 nm, and even 45nm for 300 mm wafers. But process noise greatly impacts the CD uniformity, especially etching bias and metrology noise. To achieve a CD uniformity of below 3 nm for 300 mm post-etch wafers, the metrology noise and process noise must be reduced and compensated for. In this paper, we demonstrate spectroscopic ellipsometry CD with the advantages of high stability and high accuracy to get CD information precisely, and high sensitivity to monitor PEB temperature and exposure energy fine variation in order to compensate for the etching bias.
This study focuses on the feasibility of minimizing the CD uniformity of post-etch wafers by ADI CD compensation for a 300 mm leading-edge fab. Because the CD uniformity of after-development inspection (ADI) wafers from a leading-edge lithographic tool could be in the range of only 3 nm, it is very challenging to reveal the true CD signature of an ADI wafer using a metrology tool. A spectroscopic ellipsometry based metrology tool, SpectraCD, was used in this study. In order to make sure the CD signatures reported by SpectraCD reveal the true behavior of a lithographic tool, the well-published Total Test Repeatability (TTR) test was adopted. In comparison with 3 nm CD uniformity, a 0.2 nm TTR is accurate enough for this study. In addition, from more than 100 wafers produced within a week, the CD signature of ADI wafers is very stable on wafer-to-wafer and lot-to-lot bases. Basically, all the ADI wafers produced from a single post-exposure-bake plate of an exposure tool within a week show very similar CD signatures. The feasibility of reaching a CD uniformity of 3 nm for post-etch wafers will be demonstrated in this study.