Line width roughness (LWR) is one of the most critical performance indexes for low k1 ArF immersion Lithography.
Several factors are impacting LWR performance during Lithography process, such as structures, anti-reflective coating
(ARC), photoresist, baking condition, illumination condition and track process. However, the structures and ARCs are
strongly related to integration and Etch processes. The illumination conditions, including mask bias, are decided by
simulation software but the track condition usually follows the pervious node at initial step normally. Therefore, it
sometimes shows poor results because of the difference of the under-layer condition. For example, it has been uncovered
that LWR and local CD uniformity (LCDU) became worse while structure changed to Carbon-DARC-Resist (CDR)
from Multi-Layer Resist (MLR).
Generally, photoresist evaluation with baking condition optimization is a typical way to improve LWR performance. The
photoresist formulation contains photosensitive polymers, photoacid generators (PAGs), quenchers, additives, and
solvents. Based on photoresist's point of view, the first two are the most important factors of LWR performance control.
Several designs of experiments (DOEs) were planned with polymers, PAGs, and PEB conditions. The target is to achieve
LWR of CDR under the result of MLR.
In this paper, Polymer DOE1 and its statistical analyses have finished. Compared to de-composition efficiency of each
unit, small protection unit and PEB effect are the most important factors, and bulky protection unit shows less influence
for LWR improvement. Small protection unit is more important than bulky protection unit, and high Ea monomers of
both are good for LWR. Based on previous experiences, we have chosen the acid diffusion length / amount of PAG and
PEB temperature for PAG DOE2 plan. Higher PEB is the most effective to LWR. Shorter diffusion length PAG with
fewer loading amounts is better for MEEF and EL by DOE2 result. The final DOE3 is combined by optimized polymers
by DOE1 and optimized PAG by DOE2. The polymer is used DOE1 Tr2, DOE1 Tr4, and estimated new polymer by
DOE1 result, and the PAG is chosen shorter diffusion PAG-O with the split of loading amount and PEB temperature.
Based on the statistical analyses of DOE3 result, higher PEB temperature is still the most effective to LWR, and new
polymer and DOE1 Tr2 polymer are better for LWR reduction. However, higher PEB temperature would suffer a little
bit of DOF, EL, and MEEF.
In order to achieve the lower LWR, it needs to use DOE1 Tr2 polymer with higher PEB, but insufficient DOE and
MEEF would get at the same time. New polymer by DOE1 combined fewer PAG-O loading amount with lower PEB
could get slower sensitivity for all Litho index's requirements. Through DOE works, we found out the volume of
protection unit and PEB were key factors for good LWR. However, these factors are trades off DOF, EL, and MEEF
against LWR, and they need to optimize for the best balanced Litho performances.
Double Patterning Technology (DPT) was commonly accepted as the major workhorse beyond water immersion
lithography for sub-38nm half-pitch line patterning before the EUV production. For dense hole patterning, classical DPT
employs self-aligned spacer deposition and uses the intersection of horizontal and vertical lines to define the desired hole
patterns. However, the increase in manufacturing cost and process complexity is tremendous. Several innovative
approaches have been proposed and experimented to address the manufacturing and technical challenges.
A novel process of double patterned pillars combined image reverse will be proposed for the realization of low cost
dense holes in 30nm node DRAM. The nature of pillar formation lithography provides much better optical contrast
compared to the counterpart hole patterning with similar CD requirements. By the utilization of a reliable freezing
process, double patterned pillars can be readily implemented. A novel image reverse process at the last stage defines the
hole patterns with high fidelity.
In this paper, several freezing processes for the construction of the double patterned pillars were tested and compared,
and 30nm double patterning pillars were demonstrated successfully. A variety of different image reverse processes will
be investigated and discussed for their pros and cons. An economic approach with the optimized lithography
performance will be proposed for the application of 30nm DRAM node.
Double exposure (DE) and double patterning (DP) have emerged as leading candidates to fill the technology gap
between water immersion and EUV lithography. Various approaches of them are proposed to achieve 3x-nm half-pitch
dense lines and beyond. Both DE with two resist processes and double patterning (DP) require two separate exposures,
and they are faced very tight overlay margin by the scanner tool. By contrast, self-aligned double patterning (SADP)
requires one exposure only, and provides high feasibility for 3x-nm node at this moment. However, a sequential order of
multiple non-lithographic steps (film deposition, etch, and CMP) cause a complicated and expensive process of SADP.
Instead of using complicated sacrificial layers, the spacers are directly formed at the sidewall of the resist patterns by
low-temperature CVD deposition or spin on sidewall (SoS) material coating. In this paper, lower cost-of-ownership of
SoS material are studied for SADP process.
In this paper, we will describe the principle and the design concerns with and without PFOS of TARC materials, and then make a comparison of TARC and organic bottom anti-reflective coating (BARC) which are both anti-reflective coating materials. In our discussions, we will sort the TARC applications, and then discuss the behavior of post-exposure bake (PEB) delay with and without TARC process. After that, we will discuss the material issues which we are faced of Non-PFOS TARCs, such as material being frozen during shipping process, coating performance etc. Then, we will demonstrate the Litho performances and defect results of actual Non-PFOS TARC materials. Finally, we will summarize the evaluation results of Non-PFOS TARC materials.
Due to the existing problems and delay of 157nm lithography tool, extension of the ArF (193nm) lithography process with resolution enhancement techniques (RET) should be considered for the 65nm generation lithography and beyond. The mature double-exposure lithography process based on dark-field alternating phase-shift mask (PSM) is one of the promising RET candidates, which is proven to be one of the production-ready strong phase-shifting techniques for current and future IC generations. In this paper, poly gate patterning with the minimum pitch of 160nm has been demonstrated with high numeric aperture (NA) and small partial coherence of ArF lithography along with a dark-field alternating PSM. For poly gate patterning of 65nm generation, optimum illumination settings are found for minimum pitch of 160nm. Through-pitch common process windows for gates with 65nm after-development-inspection (ADI) critical dimension (CD) at minimum pitch of 160nm can be reached larger than 0.30um depth of focus (DOF), which can be used for 65nm node production. Through-pitch proximity can be compensated by optical proximity correction (OPC). Line edge roughness (LER) can be improved a little by this dark-field alternating PSM technique. LER is found of strong aerial image contrast dependency. Shifter width is also chosen as optimum value to obtain the largest process windows and minimize the phase conflicts. 193nm Hi-NA or liquid immersion lithography is suggested to push the alternating PSM resolution limitation.
Each new technology node tests the limits of optical lithography. As exposure wavelength is reduced, new imaging techniques are needed to maximize resolution capabilities. The phase shift mask (PSM) is one such technique that is utilized to push the limits of optical lithography. Altering the optical phase of the light that transmits through a photo mask can increase the resolution of a lithographic image significantly. There are several types of phase shift mask and each has a general charateristic in which some transparent area of the mask are given 180° shift in optical phase relative to other nearby transparent areas. The interaction of the aerial images between two features with a relative phase difference of 180° create interference regions that can be used to printed images much closer together and with an increased depth of focus than that of a standard chrome-on-glass mask. An AAPSM is fabricated using a subtractive process in which the quartz substrate is etched to a given depth to produce the desired phase shift. However, intensity imbalances between the etched and non-etched regions due to sidewall scattering can cause resolution, phase and placement errors on the wafer. One method to balance the transmission is 40 nm undercut with 16 nm shifter width bias. Based on our previous study, 40 nm undercut with 16 nm shifter width bias showed an improved balance of intensities between the etched and non-etched regions. The object of this experiment is to implement the AAPSM with 40 nm undercut and 16 nm shifter width bias in SRAM product and the exposure wavelength is 193 nm. The main purpose is to proof the technology of AAPSM with 40 nm undercut and 16 nm shifter width bias in real product. Also verifying all issue of AAPSM in production. In this study, the image imbalance has been corrected via 40 nm undercut and 16 nm shifter width bias, and the DOF of AAPSM for wafer print performance is larger than binary mask. The DOF of AAPSM is about 0.5 μm and the conventional binary mask is 0.3μm.
In our previously published work, we investigated alternating-aperture PSM image intensity imbalance as function of various mask and optical parameters using rigorous electro-magnetic field (EMF) simulations. Results suggested that the imbalance could be effectively compensated through application of an optimized combination of undercut and a constant phase-shifter bias. In the effort of development and implementation of a production-ready image imbalance correction methodology, it is important to validate the accuracy of simulation-based predictions through correlation of results to experimental data. For this purpose, a test reticle containing various mask parameters as variables was designed and manufactured. The experimental data was obtained from SEM measurements of the exposed wafers, and results were compared to rigorous EMF simulation data. Based on results obtained, we propose and validate an image imbalance correction methodology to be implemented within the framework of the PSM - OPC manufacturing flow.
An extended 248nm lithography process with alternating phase-shift masks (PSMs) and etch-trimming techniques has produced 50nm gate critical dimensions (CDs). Well-controlled CD uniformity and line-end edge roughness (LER) are also demonstrated in this work. The primary factor in the improvement of through-pitch proximity bias was phase shifter width. With optimum shifter width, where pitches are greater than 600 nm, a through-pitch proximity bias of less than 10 nm can be obtained. Photoresist also has a significant role in implementing alternating PSMs, requiring high activation energy and suitable thickness. Soft-bake and post-bake temperatures were determined to enlarge the depth-of-focus (DOF). The forbidden pitch effect was enhanced to constrain the common process window after optical proximity correction (OPC) had been implemented. However, proximity bias can be kept constant with changeable diffusion length due to the through-pitch CD profiles, all isolated like. Improvement of through-focus CD at the forbidden pitch was examined by optimizing diffusion length; the common process window can be improved by 25%. All process results, including line-end roughness, DOF, exposure latitude, well-controlled CD uniformity, and through-pitch proximity bias, showed that 248 nm photolithography with alternating phase shifting mask could meet the requirements of 100nm node application.