Critical edge placement margins continue to shrink in advanced designs, Over the years, various methods have been used to quantify the lithographic “process window”, often in terms of allowable CD variation. Ultimately however, what is of most interest is the margin for chip failure, either due to hard pinching, bridging, or pattern collapse of a single layer, or interlayer critical edge placement errors. The latter could include insufficient overlap between layers such as metal and via, or unwanted bridging of patterns between layers. We present here a framework for estimating the failure rate for any individual feature given an assumed manufacturing distribution of primary patterning variables such as dose, focus, mask dimension, and perhaps overlay. If the failure rate for all features within the die is known, then by extension the failure rate for the entire die can be known. Since estimating the process window exhaustively for all in-die locations is not possible, we first identify process window limiting features, then utilize this knowledge to estimate overall die failure rates. This method can account for both systematic failure of an individual feature instance as well as stochastic failure for repeating patterns.
Finding the true on-product hot spots (patterning defects) by High Volume Manufacturing (HVM) inspection tools is increasingly challenging as the process window margin shrinks. It is a common practice nowadays to use Optical Rule Check (ORC) results by computation lithography to provide “care areas” to increase the signal to noise level of the inspection tool, thus improving the detection accuracy. The care area defined by the traditional method of contour-based process window checks may not be good enough. There are cases where real yield killers were not caught by contour-based checks, resulting in missing errors during wafer inspection as well. In this paper, we expand the traditional process window checks to a broader lithographic spectrum. The method allows us to utilize additional limiters such as max intensity, contrast, and NILS checks in combination with normal CD-based checks such as bridge, pinch, or process window bands to achieve higher accuracy in failure locations. This compound check will be trained using existing on product failure data obtained from low and high resolution wafer inspection as well as eTest and yield data. The combination of contour and intensity-based checks is demonstrated to be more effective in capturing the wafer hot spots for new products. The various usage models of such enhanced ORC will also be discussed.
In previous work, we have described how EUV scanner aberrations can be adequately simulated and corrected in OPC across the slit to deliver excellent edge placement control. The problem is that the level of aberration variability from tool to tool is currently quite significant and leads to uncorrectable edge placement errors if OPC is done using one tool while exposure happens on a different tool. In this study, we examine the impact of such edge placement errors for single patterning EUV exposure of metal and via layers with variable aberrations in projection lens systems. Two-layer combined CD and overlay edge placement hotspots can be compounded by aberrations which impact CDs and image shifts, and do so differently depending upon design pattern and pupil fill. Aberration values from current 3300 / 3350 EUV scanners are used and compared to hypothetical ideal tool with no aberrations and demonstrate very significant uncorrectable edge placement errors with current aberrations levels. The net result is a significant reduction in the metal-via combined CD-overlay process window.
Edge placement error (EPE) was a term initially introduced to describe the difference between predicted pattern contour edge and the design target. Strictly speaking this quantity is not directly measurable in the fab, and furthermore it is not ultimately the most important metric for chip yield. What is of vital importance is the relative EPE (rEPE) between different design layers, and in the era of multi-patterning, the different constituent mask sublayers for a single design layer. There has always been a strong emphasis on measurement and control of misalignment between design layers, and the progress in this realm has been remarkable, spurned in part at least by the proliferation of multi-patterning which reduces the available overlay budget by introducing a coupling of alignment and CD errors for the target layer. <p> </p>In-line CD and overlay metrology specifications are typically established by starting with design rules and making certain assumptions about error distributions which might be encountered in manufacturing. Lot disposition criteria in photo metrology (rework or pass to etch) are set assuming worst case assumptions for CD and overlay respectively. For example poly to active overlay specs start with poly endcap design rules and make assumptions about active and poly lot average and across lot CDs, and incorporate general knowledge about poly line end rounding to ensure that leakage current is maintained within specification. This worst case guard banding does not consider specific chip designs, however and as we have previously shown full-chip simulation can elucidate the most critical "hot spots" for interlayer process variability comprehending the two-layer CD and misalignment process window. It was shown that there can be differences in X versus Y misalignment process windows as well as positive versus negative directional misalignment process windows and that such design specific information might be leveraged for manufacturing disposition and control schemes.<p> </p> This paper will further investigate examples of via-metal model-based analysis of CD and overlay errors. We will investigate both single patterning and double patterning. For single patterning, we show the advantage of contour to contour simulation over contour to target simulation, and how the addition of aberrations in the optical models can provide a more realistic PW window for edge placement errors. For double patterning, the interaction of 4 layer CD and misalignment errors is very complex, but we illustrate that not only can full-chip verification identify potential rEPE hotspots, the OPC engine can act to mitigate such hotspots and enlarge the overall combined CD-overlay rEPE process window.
In-line CD and overlay metrology specifications are typically established by starting with design rules and making certain assumptions about error distributions which might be encountered in manufacturing. Lot disposition criteria in photo metrology (rework or pass to etch) are set assuming worst case assumptions for CD and overlay respectively. For example poly to active overlay specs start with poly endcap design rules and make assumptions about active and poly lot average and across lot CDs, and incorporate general knowledge about poly line end rounding to ensure that leakage current is maintained within specification. There is an opportunity to go beyond generalized guard band design rules to full-chip, design-specific, model-based exploration of worst case layout locations. Such an approach can leverage not only the above mentioned coupling of CD and overlay errors, but can interrogate all layout configurations for both layers to help determine lot-specific, design-specific CD and overlay dispositioning criteria for the fab. Such an approach can elucidate whether for a specific design layout there exist asymmetries in the response to misalignment which might be exploited in manufacturing. This paper will investigate an example of two-layer model-based analysis of CD and overlay errors. It is shown, somewhat non-intuitively, that there can be small preferred misalignment asymmetries which should be respected to protect yield. We will show this relationship for via-metal overlap. We additionally present a new method of displaying edge placement process window variability, akin to traditional CD process window analysis.
As EUV Lithography is not ready yet for sub-20nm node manufacturing, ArF immersion lithography must extend its capability. Among various double patterning techniques already explored, Litho-Etch-Litho-Etch (LELE) is one of the main streams considered today to continue scaling at 20nm and below. Our paper presents an application of a new OPC algorithm designed to ensure a successful double patterning process at 20nm node. A novel OPC technique was applied to 20nm contact and M1 layers. It is intended for both double and multi-patterning lithography technologies providing model based capability for concurrent correction of the split layouts ensuring a robust stitching overlap of the cut features and preventing inter-mask bridging. We have also developed an OPC verification methodology for DP failures due to dose, focus, mask and overlay errors. One of the most critical challenges of DP technology is: ensuring sufficient stitching of the cut design shapes and preventing a risk of inter-mask shape bridging. This problem is rapidly exacerbated by the overlay error. It is demonstrated that the new OPC algorithm results in enhanced stitching overlap and a good space control between inter-mask shapes, thus, minimizing DP process implications on circuit reliability.
Model-based Optical Proximity Correction (OPC) usually takes into consideration optical and resist process
proximity effects. However, the etch bias proximity effect usually can not be completely eliminated by etch process
optimization only and needs to be compensated for in OPC flow for several critical layers. Since the understanding of
the etch process effect is getting better and accurate etch bias modeling is available now, lithographers start to migrate
from rule-based correction to model-based correction. Conventionally when etch bias is considered in model-based
correction, optical/resist/etch effect is corrected in one step by using the input layout as the final etch target. In this
paper, we proposed a new flow in which etch and optical/resist process effect are separated in both model calibration and
layout correction. This double separation allows easier control over etch and resist target, resulting in drastic reduction
of OPC runtime. In addition it enables post-OPC verification at both resist and etch level. Advantages of the new
integrated model-based retarget/OPC flow in RET implementation are also discussed.
Sub-resolution assist features (SRAFs) or scatter bars (SBs) have steadily proliferated through IC
manufacturer data preparation flows as k<sub>1</sub> is pushed lower with each technology node. The use of this
technology is quite common for gate layer at 130 nm and below, with increasingly complex geometric rules
being utilized to govern the placement of SBs in proximity to target layer features. Recently, model based
approaches for placement of SBs has arisen. In this work, the variety of rule-based and model-based SB
options are explored for the gate layer by using new characterization and optimization functions available
in the latest generation of correction and OPC verification tools. These include the ability to quantify
across chip CD control with statistics on a per gate basis. The analysis includes the effects of defocus,
exposure, and misalignment, and it is shown that significant improvements to CD control through the full
manufacturing variability window can be realized.
Inverse microlithography solves problem of finding the best mask to print target layout. We present theoretical analysis
of objective functions and algorithms that are used for inversion. We analyze complexity, speed and limitations of the
In our continued pursuit to keep up with Moor's Law we are encountering lower and lower k1
factors resulting in increased sensitivity to lithography / OPC un-friendly designs, mask rule
constraints and OPC setup file errors such as bad fragmentation, sub-optimal site placement, and
poor convergence during the OPC application process. While the process has become evermore
sensitive and more vulnerable to yield loss, the incurred costs associated with such losses is
continuing to increase in the form of higher reticle costs, longer cycle times for learning, increased
costs associated with the lithography tools, and most importantly lost revenue due to bringing a
product to market late. This has resulted in an increased need for virtual manufacturing tools that
are capable of accurately simulating the lithography process and detecting failures and weak points
in the layout so they can be resolved before committing a layout to silicon and / or identified for
inline monitoring during the wafer manufacturing process. This paper will attempt to outline a
verification flow that is employed in a high volume manufacturing environment to identify, prevent,
monitor and resolve critical lithography failures and yield inhibitors thereby minimizing how much
we succumb to the aforementioned semiconductor manufacturing vulnerabilities.
Sub-resolution assist feature (SRAF) is widely used to improve lithographic performance. Rule-based SRAF insertion has been working well for one dimensional cases but becomes quite complex for 2-dimensional arbitrary layout. In addition, the best rule generation involves a large amount of simulation and empirical data collection. Therefore model-based SRAF insertion is much more desirable especially for 65nm node and below. In this work we use the newly developed pixel inversion method for a true model-based SRAF insertion. We'll extend our work from contact layer to lines and spaces layer to demonstrate the capability of this method for all critical layers of 65nm node. This method will be used in combination with model-based OPC to achieve the required overlapping process window and CD control. Furthermore, the manufacture issues such as mask making time and mask inspection will be examined and reported.
Besides models describing the exposure tool optical system, lumped parameter resist models are the other important model used during OPC. This combination is able to deliver the speed and accuracy required during OPC. Lumped parameter resist models are created by fitting a polynomial to empirical data. The parameters of this polynomial are usually image parameters (maximum and minimum intensity, slope, curvature) taken from the optical simulation for each measured structure. During calibration of such models, it is very important to pay attention to the parameter space covered by the calibration pattern used. We analyze parameter space coverage for standard calibration patterns, real layout situation post OPC correction as well as pre OPC correction. Taking this one step further, the influence of parameter space coverage during model calibration on OPC convergence is also studied.
SMIC is a pure-play IC foundry, as foundry culture Turn-Around Time is the most important thing FABs concern about. And aggressive tape out schedule required significant reduction of GDS to mask flow run time. So the objective of this work is to evaluate an OPC methodology and integrated mask data preparation flow on runtime performance via so-called 1-IO-tape-out platform. By the way, to achieve fully automated OPC/MDP flow for production. To evaluate, we choose BEOL layers since they were the ones hit most by runtime performance -- not like FEOL, for example, Poly to CT layers there're still some non-critical layers in the between, OPC mask makings & wafer schedules are not so tight. BEOL, like M2, V2,then M3 V3 and so on, critical layer OPC mask comes one by one continuously. Hence, that's why we pick BEOL layers. And the integrated flow we evaluated included 4 layers of metal with MB-OPC and 6 layers of Via with R-B OPC. Our definition of success to this work is to improve runtime performance at least of larger than 2x. At meantime, of course, we can not sacrifice the model accuracy, so maintaining equal or better model accuracy and OPC/mask-data output quality is also a must. For MDP, we also test the advantage of OASIS and compared with GDS format.
To shorten the turn around time and reduce the amount of effort for SRAF insertion and optimization on any arbitrary layout, a new model-based SRAF insertion and optimization flow is developed. It is based on the pixel-based mask optimization technique  to find the optimal mask shapes that result in the best image contrast. The contrast-optimized mask is decomposed into main features and assist features. The decomposed assist features are then run through a simplification process for shot count reduction to improve mask writing throughput. Model-based Optical Proximity Correction (OPC) is applied finally to achieve required pattern fidelity for the current technology. In this flow, main features and assist features are allowed to be optimized simultaneously such that the effect of SRAF optimization and Optical Proximity Correction (OPC) are achieved. Since the objective of the mask optimization is the image fidelity, and there is no light coming through assist features (in dark field case), the assist features were ensured not to print even with high dose. The results on 65nm/contact layer showed this approach greatly reduced the total time and effort required for SRAF placement optimization compared to rule-based method, with better lithographic performance for various layout types when compared to rule-based approach.
Using a commercialized product Calibre OPC platform, optical and process models were built that accurately predict wafer-level phenomena for a sub-90nm poly process. The model fidelity relative to nominal wafer data demonstrates excellent result, with EPE errors in the range of ±2nm for pitch features and ±7 for line-end features. Furthermore, these models accurately predict defocus and off-dose wafer data. Overlaying SEM images with model-predicted print images for critical structures shows that the models are stable and accurate, even in areas especially prone to pinching or bridging. In addition, process window ORC is shown to identify potential failure points within some representative designs, allowing the mask preparation shop to easily identify these areas within the fractured data. And finally, the data and images of mask hotspots will be shown and compared down to wafer level.
It is becoming more and more difficult to ensure robust patterning after OPC due to the continuous reduction of layout dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must guarantee high imaging fidelity throughout the entire range of normal process variations. The techniques of Mask Rule Checking (MRC) and Optical Rule Checking (ORC) have become mandatory tools for ensuring that OPC delivers robust patterning. However the first method relies on geometrical checks and the second one is based on a model built at best process conditions. Thus those techniques do not have the ability to address all potential printing errors throughout the process window (PW). To address this issue, a technique known as Critical Failure ORC (CFORC) was introduced that uses optical parameters from aerial image simulations. In CFORC, a numerical model is used to correlate these optical parameters with experimental data taken throughout the process window to predict printing errors. This method has proven its efficiency for detecting potential printing issues through the entire process window . However this analytical method is based on optical parameters extracted via an optical model built at single process conditions. It is reasonable to expect that a verification method involving optical models built from several points throughout PW would provide more accurate predictions of printing errors for complex features. To verify this approach, compact optical models similar to those used for standard OPC were built and calibrated with experimental data measured at the PW limits. This model is then applied to various test patterns to predict potential printing errors. In this paper, a comparison between these two approaches is presented for the poly layer at 65 nm node patterning. Examples of specific failure predictions obtained separately with the two techniques are compared with experimental results. The details of implementing these two techniques on full product layouts are also included in this study.
Use of simulation-based printing verification prior to mask tapeout has become standard practice for mask layers printed with low-k1 lithography processes. At 90nm and above, this methodology has proven beneficial and sufficient for guaranteeing a usable mask. However, it is anticipated that at 65nm and below, a simulation at a single point within the process window may fail to capture all important marginal areas of a mask prior to tapeout. Modern lithography simulation tools are proven capable of accurately predicting printing behavior through process window. Unfortunately, due to long run times, use of such tools is restricted to small simulation areas. Recent developments in vectorial thin-film OPC models have enabled full process window prediction on large product die. Although such models are extremely fast compared to conventional lithography simulation tools, the prospect of simulating a full chip at multiple dose and focus points is quite daunting. In an effort to reduce the expected longer run times when simulating full chips at multiple focus and dose conditions, we have developed two flows which reduce the total run time enormously. These so-called pre-targeting flows are explained, and the limitations and future prospects of the flows are described.
Mask making yield is seriously affected by un-repairable mask defects. Up to now, there is only one size specification for critical defects, which has to be applied to any defect found. Since recently, some mask inspection tools offer the capability to inspect different features on one mask with different sensitivity. Boolean operations can be used to segregate mask features into more and less critical. In this paper we show the MEEF (Mask Error Enhancement Factor), which determines from the mask / wafer pattern transfer the actual effectiveness of mask errors, as an objective and relatively easily determinable parameter to assess the printability of mask defects. Performing OPC, a model-based OPC tool is aware of the MEEF, and can also provide the capability for the additional information handling, which is needed to supply the mask maker with a set of data layers of different defect printability for one mask layer.
In this paper, we present a new technique (Critical Failure ORC or CF-ORC) to check the robustness of the structures created by OPC through the process window. The full methodology is explained and tested on a full chip at the 90- nm node. Improvements compared to standard ORC/MRC techniques will be presented on complex geometries. Finally, examples of concrete failure predictions are given and compared to experimental results.
In conventional Optical and Process Correction (OPC), models are calibrated with the CD measurement from the “good” printable patterns. Predictions of process window loss are based on extrapolation from the “good” region into the failure region. The extrapolation is always a less accurate process than interpolation. In this paper, we utilize the experimental pass/fail data to build models that accurately identify and predict printing failures. We developed a methodology and a formal apparatus for failure modeling. It is found that two or more aerial image shape parameters are required to describe all failure mechanisms for a sub-100nm process. This empirical failure model is currently applied to Optical Rule Checking (ORC) of the post-OPC layout. It also can be used to constrain layout corrections in the future.