All chipmakers understand that variability is the adversary of any process and reduction is essential to improving yield which translates to profit. Aggressive process window and yield specifications necessitate tight inline variation requirements on the DUV light source which impact scanner imaging performance. Improvements in reducing bandwidth variation have been realized with DynaPulse™ bandwidth control technology as significant reduction in bandwidth variation translates to a reduction in CD variation for critical device structures.
Previous work on a NAND Via layer has demonstrated an improvement in process capability through improve source and mask optimization with greater ILS and reduced MEEF that improved CDU by 25%. Using this Via layer, we have developed a methodology to quantify the contribution in an overall CDU budget breakdown. Data from the light source is collected using SmartPulse™ allowing for the development of additional methodologies using predictive models to quantify CD variation from Cymer’s legacy, DynaPulse 1 and DynaPulse 2 bandwidth control technologies. CD non-uniformities due to laser bandwidth variation for lot to lot, wafer to wafer, field to field and within field is now available based on known sensitivities and modeled. This data can assist in understanding the contribution from laser bandwidth variation in global and local CDU budgets.
Over the years, lithography engineers continue to focus on CD control, overlay and process capability to
meet current node requirements for yield and device performance. Use of ArFi lithography for advanced
process nodes demands challenging patterning budget improvements in the range of 1/10 nm especially
for interconnect layers.<sup>(1) </sup>Previous experimental and simulation based investigations into the effects of
light source bandwidth on imaging performance have provided the foundation for this work.<sup>(2-6) </sup>The
goal from the light source manufacturer is to further enable capability and reduce variation through a
number of parameters.(<sup>7-10)</sup>
In this study, the authors focus on the increase in image contrast that Source Mask Optimization (SMO)
and Optical Proximity Correction (OPC) models deliver when comparing 300 fm and 200 fm light source
E95% bandwidth. Using test constructs that follow current N7 / N5 ground rules and multiple pattern
deconstruction rules, improvements in exposure latitude (EL), critical dimension (CD) and mask error
enhancement factor (MEEF) performance are observed when SMO and OPC are optimized for 200 fm
light source bandwidth when compared with the standard 300 fm bandwidth. New SMO-OPC flows will
be proposed that users can follow to maximize process benefit. The predicted responses will be
compared with the experimental on wafer responses of 7 nm features to lower light source bandwidth.
As ArF immersion lithography continues to be extended by adopting multi-patterning techniques, imaging requirements continue to become more stringent <sup>[1-3]</sup>. For multiple patterning based logic devices, the optimal printability is not only driven by the optimization of the optical proximity correction (OPC), but also by complex process factors, such as resist, exposure tool, and mask-related error performance levels. In addition the light source plays a crucial role; it has been widely demonstrated <sup>[4-8]</sup> how changes in the E95 bandwidth can significantly lead to changes in on wafer patterning due image contrast changes. Cymer has developed novel computational and experimental approaches to enable process characterization studies <sup>[9-11]</sup>. Using these techniques, simulations were used to assess how E95 bandwidth changes can erode the CDU budget on ≤ 20 nm logic features. Using the results of these simulations, experimental conditions were defined to study the on wafer impact of light source performance on an imec N10 Logic-type test vehicle via six different Metal 1 Logic features. The imaging metrics used to track patterning response are process window (PW), line width roughness (LWR), and local critical dimension uniformity (LCDU).
Double-patterning ArF immersion lithography continues to advance the patterning resolution and overlay requirements and has enabled the continuation of semiconductor bit-scaling. Over the years Lithography Engineers continue to focus on CD control, overlay and process capability to meet current node requirements for yield and device performance. Reducing or eliminating variability in any process will have significant impact, but the sources of variability in any lithography process are many. The goal from the light source manufacturer is to further enable capability and reduce variation through a number of parameters. <p> </p>Recent improvements in bandwidth control have been realized in the XLR platform with Cymer’s DynaPulse<sup>TM</sup> control technology. This reduction in bandwidth variation could translate in the further reduction of CD variation in device structures. The Authors will discuss the impact that these improvements in bandwidth control have on advanced lithography applications. This can translate to improved CD control and higher wafer yields. A simulation study investigates the impact of bandwidth on contrast sensitive device layers such as contacts and 1x metal layers. Furthermore, the Authors will discuss the impact on process window through pitch and the overlapping process window through pitch that has been investigated. These improvements will be further quantified by the analysis of statistical bandwidth variation and the impact on CD.
Given the continually decreasing k1 factor and process latitude in advanced technology nodes, it is important to fully
understand and control the variables that impact imaging behavior in the lithography process. In this joint work between
TSMC and ASML, we use model-based simulations to characterize and predict the imaging effects of these variables
and to fine-tune the scanner settings based on such information in order to achieve optimal printing results on a perreticle
basis. The scanner modeling makes use of detailed scanner characteristics as well as wafer CD measurements for
accurate model construction. Simulations based on the calibrated model are subsequently used to predict the wafer
impact of changes in tunable scanner parameters for all critical patterns in the product. The critical patterns can be
identified beforehand, either experimentally on wafer, mask or through model simulations. A set of optimized scanner
setting offsets, known as a "scanner tuning recipe" is generated to improve the imaging behavior for the critical patterns.
We have demonstrated the efficacy of this methodology for multiple-use cases with selected ASML scanners and TSMC
processes and will share the achieved improvements on defect reduction and yield improvements.
Given the decrease in k1 factor for 65nm-node lithography technology and beyond, it is increasingly important to
understand and control the variables which impact scanner imaging behavior in the lithography process. In this work, we
explore using model simulations to characterize and predict imaging effects of these variables, and then based on such
information to fine-tune the scanner settings to obtain printing results optimally matched to a reference scanner. The
scanner modeling makes use of detailed scanner characteristics as well as wafer CD measurements for accurate model
construction. To identify critically mismatched patterns on a production layout, we employ the fast full-chip simulation
capability provided by Brion's Tachyon servers. Tachyon simulations are also used to predict wafer impacts of changes
in tunable scanner parameters. A set of optimized scanner variable offsets, called a "scanner tuning recipe", is generated
to minimize overall imaging mismatch between two scanners. As a proof-of-concept, we have carried out scanner tuning
procedures on selected ASML scanners. The results show improvements more than 20% on CD offset RMS values for
2D line-end patterns, production layout patterns, and the mismatched patterns identified with the full-chip simulation.
Improvements on wafer-acceptance-test results and production yield on the to-be-tuned scanner are also observed.