According to the ITRS roadmap, semiconductor industry drives the 193nm lithography to its limits, using techniques like Double Pattern Technology (DPT), Source Mask Optimization (SMO) and Inverse Lithography Technology (ILT). In terms of considering the photomask metrology, full in-die measurement capability is required for registration and overlay control with challenging specifications for repeatability and accuracy.
Double patterning using 193nm immersion lithography has been adapted as the solution to enable 14nm technology nodes. The overlay control is one of the key figures for the successful realization of this technology. In addition to the various error contributions from the wafer scanner, the reticles play an important role in terms of considering lithographic process contributed errors. Accurate pattern placement of the features on reticles with a registration error below 4nm is mandatory to keep overall photomask contributions to overlay of sub 20nm logic within the allowed error budget.
In this paper, we show in-die registration errors using 14nm DPT product masks, by measuring in-die overlay patterns comparing with regular registration patterns. The mask measurements are used to obtain an accurate model to predict mask contribution on wafer overlay of double patterning technology.
Most fabrication facilities today use imaging overlay measurement methods, as it has been the industry’s reliable workhorse for decades. In the last few years, third-generation Scatterometry Overlay (SCOL™) or Diffraction Based Overlay (DBO-1) technology was developed, along another DBO technology (DBO-2). This development led to the question of where the DBO technology should be implemented for overlay measurements. Scatterometry has been adopted for high volume production in only few cases, always with imaging as a backup, but scatterometry overlay is considered by many as the technology of the future. In this paper we compare imaging overlay and DBO technologies by means of measurements and simulations. We outline issues and sensitivities for both technologies, providing guidelines for the best implementation of each. For several of the presented cases, data from two different DBO technologies are compared as well, the first with Pupil data access (DBO-1) and the other without pupil data access (DBO-2). Key indicators of overlay measurement quality include: layer coverage, accuracy, TMU, process robustness and robustness to process changes. Measurement data from real cases across the industry are compared and the conclusions are also backed by simulations. Accuracy is benchmarked with reference OVL, and self-consistency, showing good results for Imaging and DBO-1 technology. Process sensitivity and metrology robustness are mostly simulated with MTD (Metrology Target Designer) comparing the same process variations for both technologies. The experimental data presented in this study was done on ten advanced node layers and three production node layers, for all phases of the IC fabrication process (FEOL, MEOL and BEOL). The metrology tool used for most of the study is KLA-Tencor’s Archer 500LCM system (scatterometry-based and imaging-based measurement technologies on the same tool) another type of tool is used for DBO-2 measurements.
Finally, we conclude that both imaging overlay technology and DBO-1 technology are fully successful and have a valid roadmap for the next few design nodes, with some use cases better suited for one or the other measurement technologies. Having both imaging and DBO technology options available in parallel, allows Overlay Engineers a mix and match overlay measurement strategy, providing back up when encountering difficulties with one of the technologies and benefiting from the best of both technologies for every use case.
The performance of overlay metrology as total measurement uncertainty, design rule compatibility, device correlation, and measurement accuracy has been challenged at the 2× nm node and below. The process impact on overlay metrology is becoming critical, and techniques to improve measurement accuracy become increasingly important. We present a methodology for improving the overlay accuracy. A propriety quality metric, Qmerit, is used to identify overlay metrology measurement settings with the least process impacts and reliable accuracies. Using the quality metric, a calibration method, Archer self-calibration, is then used to remove the inaccuracies. Accuracy validation can be achieved by correlation to reference overlay data from another independent metrology source such as critical dimension–scanning electron microscopy data collected on a device correlated metrology hybrid target or by electrical testing. Additionally, reference metrology can also be used to verify which measurement conditions are the most accurate. We provide an example of such a case.
One of the main issues with accuracy is the bias between the overlay (OVL) target and actual device OVL. In this study, we introduce the concept of device-correlated metrology (DCM), which is a systematic approach to quantify and overcome the bias between target-based OVL results and device OVL values. In order to systematically quantify the bias components between target and device, we introduce a new hybrid target integrating an optical OVL target with a device mimicking critical dimension scanning electron microscope (CD-SEM) target. The hybrid OVL target is designed to accurately represent the process influence on the actual device. In the general case, the CD-SEM can measure the bias between the target and device on the same layer after etch inspection (AEI) for all layers, the OVL between layers at AEI for most cases and after develop inspection for limited cases such as double-patterning layers. The results have shown that for the innovative process compatible hybrid targets the bias between the target and device is small, within the order of CD-SEM noise. Direct OVL measurements by CD-SEM show excellent correlation between CD-SEM and optical OVL measurements at certain conditions. This correlation helps verify the accuracy of the optical measurement results and is applicable for the imaging base OVL method using several target types advance imaging metrology, advance imaging metrology in die OVL, and the scatterometrybase OVL method. Future plans include broadening the hybrid target design to better mimic each layer process conditions such as pattern density. Additionally, for memory devices we are developing hybrid targets which enable other methods of accuracy verification.
Overlay metrology performance as Total Measurement Uncertainty (TMU), design rule compatibility, device correlation and measurement accuracy are been challenged at 2x nm node and below. Process impact on overlay metrology becoming critical, and techniques to improve measurement accuracy becomes increasingly important. In this paper, we present an innovative methodology for improving overlay accuracy. A propriety quality metric, Qmerit, is used to identify overlay metrology measurement settings with least process impacts and reliable accuracies. Using the quality metric, an innovative calibration method, ASC (Archer Self Calibration) is then used to remove the inaccuracies. Accuracy validation can be achieved by correlation to reference overlay data from another independent metrology source such as CDSEM data collected on DCM (Device Correlated Metrology) hybrid target or electrical testing. Additionally, reference metrology can also be used to verify which measurement conditions are the most accurate. In this paper we bring an example of such use case.
As overlay margins shrink for advanced process nodes, a key overlay metrology challenge is finding the measurement conditions which optimize the yield for every device and layer. Ideally, this setup should be found in-line during the lithography measurements step. Moreover, the overlay measurement must have excellent correlation to the device electrical behavior. This requirement makes the measurement conditions selection even more challenging since it requires information about the response of both the metrology target and device to different process variations. In this work a comprehensive solution for overlay metrology accuracy, used by UMC, is described. This solution ranks the different measurement setups by their accuracy, using Qmerit, as reported by the Archer 500. This ranking was verified to match device overlay using electrical tests. Moreover, the use of Archer Self Calibration (ASC) allows further improvement of overlay measurement accuracy.
One of the main issues with overlay error metrology accuracy is the bias between results based on overlay (OVL) targets and actual device overlay error. In this study, we introduce the concept of Device Correlated Metrology (DCM), which is a systematic approach to quantifying and overcoming the bias between target-based overlay results and device overlay issues. For systematically quantifying the bias components between target and device, we introduce a new hybrid target integrating an optical OVL target with a device mimicking CD-SEM (Critical Dimension – Scanning Electron Microscope) target. The hybrid OVL target is designed to accurately represent the process influence found on the real device. In the general case, the CD-SEM can measure the bias between target and device on the same layer at AEI (After Etch Inspection) for all layers, the OVL between layers at AEI for most cases and at ADI (After Develop Inspection) for limited cases such as DPL (Double Patterning Lithography). The results shown demonstrate that for the new process compatible hybrid targets the bias between target and device is small, of the order of CD-SEM measurement uncertainty. Direct OVL measurements by CD-SEM show excellent correlation with optical OVL measurements in certain conditions. This correlation helps verify the accuracy of the optical measurement results and is applicable for imaging based OVL metrology methods using AIM or AIMid OVL targets, and scatterometry-based overlay methods such as SCOL (Scatterometry OVL). Future plans include broadening the hybrid target design to better mimic each layer’s process conditions such as pattern density. We are also designing hybrid targets for memory devices.