Automatic layout optimization is becoming an important component of the DfM work flow, as the number of
recommended rules and the increasing complexity of trade-offs between them makes manual optimization increasingly
difficult and time-consuming. Automation is rapidly becoming the best consistent way to get quantifiable DfM
improvements, with their inherent yield and performance benefits for standard cells and memory blocks. Takumi autofixer
optimization of Common Platform layouts resulted in improved parametric tolerance and improved DfM metrics,
while the cell architecture (size and routability) and the electrical characteristics (speed/power) of the layouts remained
intact. Optimization was performed on both GDS-style layouts for standard cells, and on CDBA (Cadence Data Base
Architecture)-style layout for memory blocks. This paper will show how trade-offs between various DfM requirements
(CAA, recommended rules, and litho) were implemented, and how optimization for memories generated by a compiler
was accomplished. Results from this optimization work were verified on 45nm design by model and rule based DfM
checking and by wafer yields.
Design-for-manufacturing (DFM) is becoming an actual design practice among IC manufacturers, designers and
EDA companies. Layout assessment by design-rule-check (DRC) using EDA tools is a common practice today to ensure
well-manufactured design geometries. Standalone DFM tools, which require iteration loops of DFM analysis and fixing,
do not fit well in design flows and are considered cumbersome. A better layout assessment method for DFM issues is
required: one that gives actionable feedback, and that can be used with automatic optimization in early design stages.
The latter is needed to avoid costly design re-spins that will consume critical time-to-market as well as use a lot of
engineering resources, reticles and wafer material costs. For example, a DFM checking tool may report the hotspot types
and locations, but this information is not sufficient for designers to decide tradeoffs between different fixing choices and
to take care of trade-off between physical and electrical design constraints at the same time. When model-based
properties are introduced such as lithographic contour, the tradeoffs between rule-based and model-based properties can
only be resolved by the automatic and concurrent optimization.
This work demonstrates a methodology of DFM scoring of layout based on preferred rules compliance, lithography
GATE printability, as well as the layout fixing. The electrical impact on gates is analyzed and showed reduced variability
(compared to nominal behavior) in gate performance. Designers can get visual feedback of the layout quality, as well as
improvement suggestions. Takumi TKE software is used to demonstrate automatic and concurrent optimization. The
method applies to both cell-level and custom designs.
DFM considerations have become an indispensable and integral part of advanced nanometer semiconductor product
designs. Traditional first-generation DFM tools have focused on functional lithography hotspot detections. While useful,
these tools offer designers few hints on the complex layout fixings and the intricate trade-off decisions required. With
these limitations, DFM layout optimization has become a tedious and inconsistent design endeavor. In addition, the long
and intense calibration cycle required for the traditional DFM models have hindered their effectiveness and timeliness.
An automatic DFM layout optimization system that performs systematic multi-objective functional and parametric DFM
optimizations at early design phase will be introduced. A calibration-lite methodology that has expedited the DFM
model set-ups will be discussed along with the silicon validation test pattern designs. Finally, both simulation and
silicon experiment results will be presented.
A new design for manufacturability (DfM) scheme with a lithography compliance check (LCC) and hot spot fixing (HSF) flow has been developed to guarantee design compliance for OPC and RET by combining lithography simulator, hot spot detector and layout modification tool. Hot spots highlighted by the LCC flow are removed by the HSF flow following modification rule consists of "Line-Sizing" (LS) and "Space-Sizing (SS)" that are resize value of line-width and space-width for the original pattern. In order to meet layout modification requirements at the pre- and post- tape out (T.O.) stages, the priorities individually set for the modification rules and the design rules, which provides flexibly to achieve the modification scheme desirable at each stage. For handling large data at a fast speed, Layout Analyzer (LA) and Layout Optimizer (LO) engines were combined with the HSF flow. LA is used to reconstruct the original hierarchy structure, clips off small parts of the layout that include hot spots from the original layout and sends those to LO in order to reduce the computational time and resource. LO optimizes the clipped off layout following the prioritized modification- and design-rules. The new DfM scheme was found to be quite effective for hot spot cleaning for 65nm node and beyond, since it was demonstrated that the HSF flow improved the lithography margin for the metal layer of 65nm node full-chip data by reducing number of hot spots to below 0.1% of original within about 12 hours, using 1CPU of commercially available workstation.