Ultra-wideband (UWB) technology dates back to early 1980s and was originally employed in radar applications. Unlike any narrowband or broadband communication systems, an UWB system does not employ any radio frequency (RF) carrier for data transmission. Instead it uses very short period electrical pulses in the order of hundreds of pico-seconds to few nano-seconds, which justifies the availability of an ultra-high bandwidth. From a hardware implementation viewpoint, UWB system design presents many challenges such as synchronisation, power limitation and receiver design. However, the design of an UWB transceiver is less complex given the fact that the RF carrier is eliminated. In an UWB transceiver, most of the processing is performed in the digital baseband while the analog front end is
responsible for amplification, filtering and quantisation. A bank of matched filters constitutes the major portion of digital baseband section in an UWB transceiver. This paper presents the design, optimisation and field programmable gate array (FPGA) implementation of the matched filter bank as an attempt to minimise the overall circuit complexity, achieve higher data rates and low power consumption in UWB radios.