In this paper, the implementations of clock and carrier recovery in digital domain are analyzed. Hardware implementation details, resources estimation and real-time results are presented. Analog-to-Digital Converters (ADC), operating at 1.25Gsa/s, and a Virtex-6 Field-Programmable Gate Array (FPGA), have been used, allowing the implementation of a real-time Quadrature Phase Shift Keying (QPSK) system operating at 1.25Gb/s. The real-time mode operation is successfully demonstrated over 80 km of Standard Single Mode Fiber (SSMF).
We perform a thorough performance and complexity analysis of a recently proposed Volterra series nonlinear equalizer (VSNE) for digital post-compensation of nonlinear fiber impairments in high-speed and long-haul coherent optical communication systems. Using a maximum absolute value selection criteria, we implement a pruning strategy for the matrix-based VSNE and compare its performance/complexity with the symmetric VSNE (symVSNE) and simpli ed VSNE (simVSNE) algorithms. The theoretical analysis is supported by simulation results obtained for a single-channel 224 Gb/s PM-16QAM transmission system with a signal propagation distance of 1920 km.