In emerging agile all-optical networks, where time division multiplexing (TDM) in the optical domain is implemented on top of wavelength-division multiplexing (WDM) to improve the network utilization and to support dynamic bandwidth demands, a control mechanism is required to handle the setup and tear down of fast flexible all-optical connections. In this paper, we propose two control protocols for WDM-TDM all-optical ring networks based on whether or not global network information is available. For the global information based protocol, we choose a periodic state-updating mechanism to confine the control message overhead within a reasonable range. For the local information based protocol, we select a backward reservation scheme for dynamic routing, wavelength and timeslot assignment (DRWTA) algorithms to prevent bandwidth overbooking. By conducting extensive numerical simulations, we investigate the impact of imprecise information on the blocking probability of the DRWTA algorithms for the two protocols. Our simulation results show that the local information based protocol outperforms the global information based protocol for metro all-optical networks where propagation delay is small compared to the service time of requests.
This paper presents a burst aggregation method for an Agile All-Photonic Network (AAPN) operating under an asynchronous burst switched mode. The model combines both the timer-based and threshold-based approaches into a single composite burst assembly mechanism. This is evaluated semi-analytically for fixed length packets and Poisson arrivals and used as a special case to verify a more general OPNET Modeler simulation. The dependence of the blocking probability on different burst aggregation parameters is observed as well. The same procedure is extended to 'encapsulate' (aggregate) variable packet length traffic into 'envelopes' (bursts) matched to the time slots in an AAPN operating in a synchronous time-slotted mode. Results are presented for an emulation of this process using real IP network traffic from the local LAN using two encapsulation methods that differ depending upon whether 'envelope' boundaries are allowed to cross constituent packets or otherwise. Bandwidth utilization was measured for different encapsulation parameters and it is confirmed that the model with the boundaries allowed to cross packets (i.e., the model with packet segmentation) is more bandwidth-efficient even if the processing delay is slightly larger. The successful operation of the emulation system suggests as well that a simple, low-cost software implementation would be suitable to perform the burst/slot aggregation process in AAPN.
In this paper, a three-stage packet switch architecture is implemented consisting of a reconfigurable optical center stage surrounded by two electronic buffering stages grouped into sectors to ease contention. A Flexible Bandwidth Provision algorithm is used to change the configuration of the optical center stage to form the requested bandwidth desired by incoming traffic. The switch is modeled by a bipartite graph built from the service matrix. The bipartite graph is decomposed by solving an edge-coloring problem and the resulting permutations are used to configure the central stage removing the requirement for a per-time slot scheduler.
Flexible Bandwidth Provision (FBP) algorithm requires dynamically reconfigurable technology readily available in programmable logic devices. The designed packet switch being a collection of discrete entities is most easily implemented on separate programmable logic devices forming electronic “islands” interconnected by photonics technology. The demonstrator itself contains 64 inputs and 64 outputs with reconfigurable central stage crossbars. The switch is a collection of input and output sectors each implemented on a single FPGA. Each sector is an 8 x 8 sub-switch with shared buffer memory. The interface between the sectors and the central stage will use VCSEL technology for O-E-O conversion. The input sectors together with the central stage form the adaptive portion of the switch configured by an embedded soft-core processor implementing the FBP algorithm of which is entity are located on an Ethernet local area network.
This switching architecture has also been simulated and results show that this architecture result in a dramatic reduction of complexity, at the price of only a modest spatial speed-up (<2).