In order to satisfy the requirements of short-wave infrared hyperspectral detection, we developed a 1024 x 512 ROIC with 30μm pixel pitch. CTIA with cascode amplifier was utilized as input stage and CDS was used for eliminating KTC noise and 1/f noise in CTIA. For this large chip with sizes up to 30mm x 20mm, it has been found that column circuit was a major bottleneck to achieve high frame frequency. A solution to solve this problem in this work is to pre-establish the signal of the column amplifier and then buffer odd and even column signals to the bus alternatively. In addition, parasitic capacitance of column-level bus was carefully lowered in layout design. The total readout rate reached 120 Mpixels/s with eight parallel output channels which allowed for a frame rate of 250 Hz.
The spectral irradiance of moonlight and air glow is mainly in the wavelength region from visible to short-wave infrared (SWIR) band. The imaging over the wavelength range of visible to SWIR is of great significance for applications such as civil safety, night vision, and agricultural sorting. In this paper, 640×512 visible-SWIR InGaAs focal plane arrays (FPAs) were studied for night vision and SWIR imaging. A special epitaxial wafer structure with etch-stop layer was designed and developed. Planar-type 640×512 InGaAs detector arrays were fabricated. The photosensitive arrays were bonded with readout circuit through Indium bumps by flip-chip process. Then, the InP substrate was removed by mechanical thinning and chemical wet etching. The visible irradiance can reach InGaAs absorption layer and then to be detected. As a result, the detection spectrum of the InGaAs FPAs has been extended toward visible spectrum from 0.5μm to 1.7μm. The quantum efficiency is approximately 15% at 0.5μm, 30% at 0.7μm, 50% at 0.8μm, 90% at 1.55μm. The average peak detectivity is higher than 2×1012 cm·Hz1/2/W at room temperature with an integrated time of 10 ms. The Visible-SWIR InGaAs FPAs were applied to an imaging system for SWIR and visible light imaging.
A low noise low power 512×256 readout integrated circuit (ROIC) based on Capacitance Trans-impedance Amplifier (CTIA) was designed in this paper. The ROIC with 30μm pixel-pitch and 70 fF integrated capacitance as normal structure and test structure capacitance from 5 to 60 fF, was fabricated in 0.5μm DPTM CMOS process. The results showed that output voltage was larger than 2.0V and power consumption was about 150mW, output ROIC noise was about 3.6E-4V which equivalent noise was 160e-, and the test structure noise was from 20e- to 140 e-. Compared the readout noises in Integration Then Readout (ITR) mode and Integration While Readout (IWR) mode, it indicated that in IWR mode, readout noise comes mainly from both integration capacitance and sampling capacitance, while in ITR mode, readout noise comes mostly from sampling capacitance. Finally the ROIC was flip-chip bonded with Indium bumps to extended wavelength InGaAs detectors with cutoff wavelength 2.5μm at 200K. The peak detectivity exceeded 5E11cmHz1/2/w with 70nA/cm2 dark current density at 200K.
A low noise high readout speed 512×128 readout Integrated circuit (ROIC) based on capacitance trans-impedance amplifier (CTIA) is designed in this paper. The ROIC is flip-chip bonded with Indium bumps to InGaAs detectors which cutoff wavelength is 1.7μm, as a hybrid structure (InGaAs FPA). The ROIC with 30μm pixel pitch and 50fF integrated capacitance, is fabricated in 0.5μm DPTM CMOS process. The results show that output noise is about 3.0E-4V which equivalent readout noise is 95e-, output voltage swing is better than 2.5V; the dynamic range of InGaAs FPA reaches 69.7dB@2ms, and the power dissipation is about 175mw. The peak detectivity of InGaAs FPA reaches 2E12cmHz1/2w-1 at 300K without TEC cooling.
A 128×128 matrix readout integrated circuit (ROIC) for 15×15 μm2 InGaAs focal plane array (FPA) is reported in this paper. Capacitive-feedback Trans-Impedance Amplifier (CTIA) and correlated double sampling (CDS) are both involved in ROIC pixel which dissipates 90nW and has a full-well-capacity (FWC) of about 78,000 e-. Noises of ROIC pixel are analyzed and distribution method of capacitors in pixel is discussed in order to obtain low-noise performance. In column buffer circuit, a new pre-charging technique is developed to realize readout rate of 20 MHz with low power consumption. The ROIC is fabricated with 0.18-μm 3.3 V mixed signal CMOS process. Test results show that the ROIC has an equivalent input noise of about 181e- and can achieve a readout rate of 20 MHz.
It is well known that In0.53Ga0.47As epitaxial material is lattice-matched to InP substrate corresponding to the wavelength from 0.9μm to 1.7μm, which results to high quality material and good device characteristics at room temperature. In order to develop the near infrared multi-spectral imaging, 512×128 pixels InGaAs Near Infrared Focal Plane Arrays (FPAs) were studied. The n-InP/i-InGaAs/n-InP double hereto-structure epitaxial material was grown by MBE. The 512×128 back-illuminated planar InGaAs detector arrays were fabricated, including the improvement of passivation film, by grooving the diffusion masking layer, the P type electrode layer, In bump condition and so on. The photo-sensitive region has the diffusion area of 23×23μm2 and pixel pitch of 30×30μm2 . The 512×128 detector arrays were individually hybridized on readout integrated circuit(ROIC) by Indium bump based on flip-chip process to make focal plane arrays (FPAs). The ROIC is based on a capacitive trans-impedance amplifier with correlated double sampling and integrated while readout (IWR) mode with high readout velocity of every pixel resulting in low readout noise and high frame frequency. The average peak detectivity and the response non-uniformity of the FPAs are 1.63×1012 cmHz1/2/W and 5.9%, respectively. The power dissipation and frame frequency of the FPAs are about 180mW and 400Hz, respectively.
Noise is a primary characteristic of an infrared focal plane array (FPA) that contributes to detection performance at
low light level. In a capacitive-feedback trans-impedance amplifier (CTIA)-based readout integrated circuit (ROIC),
reset noise can be removed by correlated double sampling (CDS). There is an exotic experimental phenomenon
that FPA noise will increase greatly if the first sampling time of CDS is less than a threshold value. A noise model
at FPA interface is presented in this paper which explains that this new kind of noise originates from incompletely
settling of CTIA preamplifier. As this noise is performed in time domains, we use transient noise simulation
technique to describe the dependence of this noise on detector pixel capacitance, integration capacitor, and some
other design parameters. Based on the theoretical model analysis and simulation results, effective design method is
obtained to reduce this kind of noise.
High frame rate imaging for applications such as meteorological forecast, motion target tracking require high-speed Read-Out Integrated Circuit (ROIC). In order to achieve 10 KHz of frame rate, this paper analyzes the bandwidth of Capacitive-feedback Trans-Impedance Amplifier (CTIA) in ROIC which is the dominant bandwidth-limiting node when interfaced with large InGaAs detector pixel capacitance of about 10pF. A small-signal model is presented to study the relationship between integration capacitance, detector capacitance, transconductance and CTIA bandwidth. Calculation and simulation results show explicitly how the series resistance at the interface restricts the frame rate of Focal Plane Arrays (FPA). In order to achieve low-noise performance at a high frame rate, this paper describes an optimal solution in ROIC design. A prototype ROIC chip (DL7) has been fabricated with 0.5-μm mixed signal CMOS process and interfaced with InGaAs detector arrays. Test results show that frame rate is above 10 KHz and ROIC noise is around 270 e-, near identical to the design value.
InGaAs near-infrared (NIR) focal plane arrays (FPA) have important applications in space remote sensing. A design of 800×2 low-noise readout integrated circuit (T800 ROIC) with a pitch of 25 μm is presented for a dual-band monolithic InGaAs FPA. Mathematical analysis and transient noise simulations have been presented for predicting and lowering the noise in T800 ROIC. Thermal noise from input-stage amplifier which plays a dominant role in ROIC is reduced by increasing load capacitor under tradeoff and a low input offset voltage in the range of ±5 mV is obtained by optimizing transistors in the input-stage amplifier. T800 ROIC has been fabricated with 0.5-μm 5V mixed signal CMOS process and interfaced with InGaAs detector arrays. Test results show that ROIC noise is around 90 μV and input offset voltage shows a good correspondence with simulation results. 800×2 InGaAs FPA has a peak detectivity (D*) of about 1.1×1012 cmHz1/2/ W, with dynamic range of above 80dB.