This paper presents the design of a CMOS 64-bit adder using threshold logic gates based on Logical Effort (LE) transistor level
delay estimation. The adder is a hybrid design, consisting of domino
logic and the recently proposed Charge Recycling Threshold Logic
(CRTL). The delay evaluation is based LE modeling of the delay of
the domino and CRTL gates. From the initial estimations, the 8-bit
sparse carry look-ahead/carry-select scheme has a delay of less than
5.5 FO4 (fan-out-of-four inverter delay), which is more than 1 FO4
delay faster than any previously published domino design.
In recent years, there has been renewed interest in Threshold Logic
(TL), mainly as a result of the development of a number of
successful implementations of TL gates in CMOS. This paper presents
a summary of the recent developments in TL circuit design.
High-performance TL gate circuit implementations are compared, and a
number of their applications in computer arithmetic operations are
reviewed. It is shown that the application of TL in computer
arithmetic circuit design can yield designs with significantly
reduced transistor count and area while at the same time reducing
circuit delay and power dissipation when compared to conventional
CMOS logic.
In recent years, there has been renewed interest in Threshold Logic (TL), mainly as a result of the development of a number of successful implementations of TL gates in silicon. Threshold Logic enables, in some instances, the design of digital integrated circuits with a significantly reduced transistor count and area. This paper addresses the important problem of designing technologically feasible parallel (m,n) counters for using TL for binary multiplication. A number of counter design techniques are reviewed and some novel parallel counter designs are presented that allow the design of area efficient 32-bit multiplier partial product reduction circuits.
Conference Committee Involvement (5)
Smart Structures, Devices, and Systems IV
10 December 2008 | Melbourne, Australia
Microelectronics: Design, Technology, and Packaging III
5 December 2007 | Canberra, ACT, Australia
Smart Structures, Devices, and Systems III
11 December 2006 | Adelaide, Australia
Microelectronics: Design, Technology, and Packaging II
12 December 2005 | Brisbane, Australia
Microelectronics: Design, Technology, and Packaging
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