In world-leading semiconductor manufacturing, the device feature size keeps on reducing and with it processes become more challenging in the next technology node. The on-product overlay budget is therefore required to reduce further. Alignment is one of the key factors in reducing overlay wafer-to-wafer variation. Due to the complexity, a holistic methodology is used to combine various alignment solutions to achieve the optimal on-product overlay performance. In this paper, we evaluated the holistic method by simulation and experiment for DUV layers. We illustrate the expected on-product overlay improvement.