Gallium oxide (Ga2O3) is a promising wide bandgap semiconductor for power electronic applications. Investigation into the conduction mechanism of Ga2O3 Schottky diodes is important for improving the device performance. In this study, the forward-biased temperature dependent current-voltage (I-V-T) characteristics of Ni/(-201) β-Ga2O3 Schottky diodes have been investigated in the temperature range of 298-473 K. The apparent barrier height (ϕ_ap) increased while the ideality factor (n) decreased with the increase in temperature. Such a temperature dependent behavior of ϕ_ap and n was explained by the inhomogeneity of ϕ_ap, which obeyed Gaussian distribution with mean barrier height of 1.8 eV and standard deviation of 201 mV. Subsequently, zero-bias barrier height (¯ϕ_B0) and Richardson constant (A*) were obtained from the slope and intercept of the modified Richardson plot as 1.18 e V and 94.04 A·cm-2·K-2, respectively. The ¯ϕ_B0 obtained from the modified Richardson plot was in good agreement with the theoretical value calculated from the work function of Ni and electron affinity of β-Ga2O3. The I-V-T characteristics of Ni/-Ga2O3 Schottky diodes can be successfully explained by the thermionic emission theory with a single Gaussian distribution of the barrier height.
Gallium nitride (GaN) based transistors have been of interest to power electronics community because of their high breakdown voltage, high sheet carrier density, and the high saturation velocity of GaN. The low switching losses of GaN enable high-frequency operation which reduces bulky passive components with negligible change in efficiency [1,2]. The most established GaN electronic devices are fabricated on the Ga-polar orientation of GaN. Recently, N-polar GaN based devices are being explored for high frequency applications due to their advantages over Ga-face, such as lower contact resistance since the 2DEG is contacted through a lower bandgap material and better electron confinement due to natural back-barrier provided by the charge inducing barrier . In this work, the first N-polar GaN current aperture vertical electron transistor is presented. The samples were grown by metal-organic chemical vapor deposition on c-plane Sapphire substrate. Mg ions were implanted at 80keV (dose: 1×〖10〗^15 〖cm〗^(-2)) into the top GaN layer, everywhere except the current aperture to form the current blocking layer. A 7 A^0 AlN to reduce alloy scattering followed by 150nm UID N-polar GaN as channel were regrown on top of the implanted structure. The 2DEG density and the mobility of the as-grown sample, determined using Hall measurement, were 1.1×〖10〗^13 〖cm〗^(-2) and 1800 〖cm〗^2/(V-S) , respectively. The CAVET showed excellent device modulation and a maximum current of 2 KA〖cm〗^(-2) at V_G=2V. The maximum transconductance per mm of source was 140 mS. The device had a very large pinch-off voltage of -14V as calculated due to the presence of high charge density in the channel.
 S. Chowdhury et al 2013 Semicond. Sci. Technol. 28 074014
 J. Millán, et al 2014 IEEE Transactions on Power Electronics, 29, 2155
 Uttam Singisettiet al 2013 IOP Semicond. Sci. Technol. 28 074006
In this work, a study of two different types of current aperture vertical electron transistor (CAVET) with ion-implanted blocking layer are presented. The device fabrication and performance limitation of a CAVET with a dielectric gate is discussed, and the breakdown limiting structure is evaluated using on-wafer test structures. The gate dielectric limited the device breakdown to 50V, while the blocking layer was able to withstand over 400V. To improve the device performance, an alternative CAVET structure with a p-GaN gate instead of dielectric is designed and realized. The pGaN gated CAVET structure increased the breakdown voltage to over 400V. Measurement of test structures on the wafer showed the breakdown was limited by the blocking layer instead of the gate p-n junction.
Al<sub>2</sub>O<sub>3</sub> has been an attractive gate dielectric for GaN power devices owing to its large conduction band offset with GaN (~2.13eV), relatively high dielectric constant (~9.0) and high breakdown electric field (~10 MV/cm). Due to exceptional control over film uniformity and deposition rate, atomic layer deposition (ALD) has been widely used for Al<sub>2</sub>O<sub>3</sub> deposition. The major obstacle to ALD Al<sub>2</sub>O<sub>3</sub> on GaN is its high interface-state density (Dit) caused by incomplete chemical bonds, native oxide layer and impurities at the Al2O3/GaN interface. Therefore, an appropriate surface pretreatment prior to deposition is essential for obtaining high-quality interface. In this study, we investigated the effect of TMA, H<sub>2</sub>O and Ar/N<sub>2 </sub>plasma pretreatment on D<sub>it</sub> and border traps (N<sub>bt</sub>). 5 cycles of TMA purge, 5 cycles of H<sub>2</sub>O purge and Ar/N<sub>2</sub> plasma pretreatment were conducted on GaN prior to deposition of ALD Al<sub>2</sub>O<sub>3</sub>. Al<sub>2</sub>O<sub>3</sub>/GaN metaloxide-semiconductor capacitors (MOSCAPs) were fabricated for the characterization of D<sub>it</sub> and N<sub>bt</sub> using UV-assisted capacitance-voltage (C-V) technique. The results show that TMA and H<sub>2</sub>O pretreatment had trivial effects on interface engineering whereas Ar/N<sub>2</sub> plasma pretreatment slightly reduced D<sup>it</sup> and significantly reduced N<sub>bt</sub>.
We report the use of sol-gel method at room ambient to grow nanoscale thin film of Ga<sub>2</sub>O<sub>3</sub> on Si surface for both surface
passivation and gate dielectric. The admittance measurements were carried out in the frequency range of 20 kHz-1 MHz
at room temperature. Voltage dependent profile of interfacial trap density (D<sub>it</sub>) was obtained by using low and high
frequency capacitance method. The capacitance (C)-voltage (V) analyses show that the structures have a low interfacial
trap density (D<sub>it</sub>) of 1x10<sup>12</sup> cm<sup>-2</sup>eV<sup>-1</sup>. The Ga<sub>2</sub>O<sub>3</sub> thin film synthesized via sol-gel method directly on devices to function
as a gate dielectric film is found to be very effective. We also present our experimental results for a number of gate
dielectric and device passivation applications.