The formation mechanism of various 193nm immersion-related defects is investigated. The experimental results are
reviewed and compared to the simulation results, which enables us to form a clear picture of how the immersion defects
are generated. Based on the understanding of defects mechanisms, a series of the defect reduction measures is proposed
for the 193nm immersion process.
Significant effort has been directed in recent years towards the realization of immersion lithography at 193nm
wavelength. Immersion lithography is likely a key enabling technology for the production of critical layers for 45nm and
32nm design rule (DR) devices. In spite of the significant progress in immersion lithography technology, there remain
several key technology issues, with a critical issue of immersion lithography process induced defects. The benefits of the
optical resolution and depth of focus, made possible by immersion lithography, are well understood. Yet, these benefits
cannot come at the expense of increased defect counts and decreased production yield. Understanding the impact of the
immersion lithography process parameters on wafer defects formation and defect counts, together with the ability to
monitor, control and minimize the defect counts down to acceptable levels is imperative for successful introduction of
immersion lithography for production of advanced DR's. In this report, we present experimental results of immersion
lithography defectivity analysis focused on topcoat layer thickness parameters and resist bake temperatures. Wafers were
exposed on the 1150i-α-immersion scanner and 1200B Scanner (ASML), defect inspection was performed using a DUV
inspection tool (UVision<sup>TM</sup>, Applied Materials). Higher sensitivity was demonstrated at DUV through detection of small
defects not detected at the visible wavelength, indicating on the potential high sensitivity benefits of DUV inspection for
this layer. The analysis indicates that certain types of defects are associated with different immersion process parameters.
This type of analysis at DUV wavelengths would enable the optimization of immersion lithography processes, thus
enabling the qualification of immersion processes for volume production.
Successful developer-soluble topcoats have to fulfill numerous requirements; specifically they have to serve as a barrier layer and be compatible with the resist. Some of the requirements and compatibility issues have been understood; others are still under-investigation by the joint efforts of lithographers and resist chemists. This paper addresses these requirements from the perspective of overall lithographic performance for developer-soluble topcoats used in 193nm water immersion lithography. We demonstrate that with the optimized combination of resist and developer-soluble topcoat 90nm 1:1 dense lines can be printed using a prototype tool, ASML AT 1150i, and a binary image mask (BIM) with a maximum depth-of-focus (DOF) of ~1.2μm. An approximate 2X DOF improvement over dry lithography that was theoretically expected has been truly demonstrated. Topcoat related defectivity as well as defect reduction efforts are also discussed.
Immersion Lithography continues to get more and more attention as a possible solution for the 45nm technology node puzzle. In 2005, there has, indeed, been a lot of progress made. It has gone from a laboratory curiosity to being one of the industry's prime contenders for the lithography technology of choice for the 45nm node. Yet a lot of work remains to be done before it's fully implemented into production. Today, there are over a dozen full field immersion scanners in R&D and pilot lines all around the world. The first full field, pre-production "Alpha" version of the ASML Twinscan AT 1150i was delivered to Albany NanoTech in August, 2004. A consortium made up of AMD, IBM, Infineon, and Micron Technology began early evaluation of immersion technology and in December of 2004, the production of the world's first Power PC microprocessor using immersion lithography, processed on this tool, was announced by IBM.
This paper will present a summary of some of the work that was done on this system over the past year. It will also provide an overview of Albany NanoTech, the facility, its capabilities, and the programs in place. Its operating model, which is heavily focused on cooperative joint ventures, is described. The immersion data presented is a review of the work done by AMD, IBM, Infineon Technologies, and Micron Technology, all members of the INVENT Lithography Consortium in place at Albany NanoTech. All the data was published and presented by the authors in much more detail at the 2005 International Symposium on Immersion Lithography, in Bruges, Belgium.
To evaluate the effect of water exposure to a resist stack a set of experiments was designed that introduce a pre- and post-exposure wetting time to a coated wafer. The ASML 1150i α-immersion scanner, integrated with a TEL-Lithius coater track, was used to investigate the formation of defects related to the extended wetting. In the first approach, wetting was achieved using a dynamic DI-water rinse in the developer module of the track. For the second approach the immersion hood was positioned over the wafer at a fixed position and time, subjecting the wafer area below the immersion hood to the flowing water. We investigated various resists and topcoats. Defect inspections were performed on these film stacks after imaging.