EUV resists, while improving steadily, generate a number of nanobridge or break defects that increases quickly as the pitch approaches 30 nm. Inline inspection methods are therefore needed to reliably detect patterning defects smaller than 20 nm. Massive e-beam metrology provides the high resolution needed to measure these defects, while remaining compatible with HVM throughput requirements. In this work, we used a direct metal (Ru) etch process, to fabricate EUV-patterned electrical structures in the 32 nm-36 nm pitch range. We demonstrate an almost one-to-one correspondence between the e-beam metrology yield of the structures, and their electrical yield. The e-beam inspection is realized with a large-field-of-view HMI eP5 e-beam system. The match between e-beam and electrical yield shows that our e-beam inspection is able to catch all electrically relevant line breaks, while excluding false flags. These results demonstrate the capability of massive e-beam inspection in predicting electrical yield.
In the next generation SAOP (Self-aligned Octuplet patterning) process, the line width and LWR (Line Width Roughness) measurement of lines with sub-10 nm is required. We have already proposed a novel method of line width and LWR measurement with sub-nanometer uncertainty by using FIB (Focused Ion Beam) processing, and TEM (Transmission Electron Microscope) images as reference metrology. In the previous report, we applied the method to SAQP features. A specimen of the SAQP FinFET line and space device is coated with carbon and cut horizontally into a thin planar sample by the FIB sampling system. The thin sample is observed by using planar-TEM. The average PSD of LWR of SAQP FinFET sample at the upper and lower positions calculated from planar-TEM images.
In this article, we apply the methodology to line width and roughness measurement of advanced features by SAOP process. The features are vertically or horizontally sliced as a thin specimen by FIB micro sampling system. LWR is calculated from the edges positions, and PSD (Power Spectrum Density) is analyzed for the reference metrology.
While the semiconductor industry has reached the high-volume manufacturing of the 7 nm technology node (N7), patterning processes for future technology nodes N5, N3 and even below, are being investigated and developed by research centers. To achieve the critical dimensions of gratings for these future technology nodes, we require multipatterning approaches, such as self-aligned double/quadruple/octuple patterning (SADP/SAQP/SAOP) and multiple litho-etch (LE) patterning, in combination with 193i lithography and even EUV lithography. These gratings need to be subsequently cut or blocked, which is typically done by one or more block masks. As the edge placement error (EPE) budget drastically decreases with decreasing critical dimensions, the standard LE block patterning scheme is not sufficient anymore. To relax the EPE budget, dedicated scaling boosters are required such as the self-aligned block scheme, which defines blocks in trenches, selectively to the neighboring trenches.
In this work we explore the different multipatterning options for lines and blocks at pitches below 20 nm. As such, we will demonstrate and compare three different patterning options to enable 16 nm pitch gratings: 193i-based SAOP, EUV-based SADP and EUV-based SAQP. Finally, we will also elaborate on a self-aligned patterning scheme which does not define lines and blocks sequentially anymore but integrates them in a mixed mode. This patterning approach (SALELE) makes use of two LE masks and two self-aligned block masks. We will present its development status at relaxed pitch (28 nm) and discuss its advantages for future technology nodes.
The semiconductor scaling roadmap shows the continuous node to node scaling to push Moore’s law down to the next generations. In that context, the foundry N5 node requires 32nm metal pitch interconnects for the advanced logic Back- End of Line (BEoL). 193immersion usage now requires self-aligned and/or multiple patterning technique combinations to enable such critical dimension. On the other hand, EUV insertion investigation shows that 32nm metal pitch is still a challenge but, related to process flow complexity, presents some clear motivations.
Imec has already evaluated on test chip vehicles with different patterning approaches: 193i SAQP (Self-Aligned Quadruple Patterning), LE3 (triple patterning Litho Etch), tone inversion, EUV SE (Single Exposure) with SMO (Source-mask optimization). Following the run path in the technology development for EUV insertion, imec N7 platform (iN7, corresponding node to the foundry N5) is developed for those BEoL layers.
In this paper, following technical motivation and development learning, a comparison between the iArF SAQP/EUV block hybrid integration scheme and a single patterning EUV flow is proposed. These two integration patterning options will be finally compared from current morphological and electrical criteria.
While the semiconductor industry is almost ready for high-volume manufacturing of the 7 nm technology node, research centers are defining and troubleshooting the patterning options for the 5 nm technology node (N5) and below. The target dimension for imec’s N5 BEOL applications is 20-24 nm Metal Pitch (MP), which requires Self-Aligned multiple (Double/Quadruple/Octuple) Patterning approaches (SAxP) in combination with EUV or immersion lithography at 193 nm. There are numerous technical challenges to enable gratings at the hard mask level such as good uniformity across wafer, low line edge/width roughness (LER/LWR), large process window, and all of this at low cost. An even greater challenge is to transfer these gratings into the dielectric material at such critical dimensions, where increased line edge roughness, line wiggling and even pattern collapse can be expected for materials with small mechanical stability such as highly porous low-k dielectrics. In this work we first compare three different patterning options for 12 nm half-pitch gratings at the hard mask level: EUV-based SADP and 193i-based SAQP and SAOP. This comparison will be based on process window, line edge/width roughness and cost. Next, the transfer of 12 nm line/space gratings in the dielectric material is discussed and presented. The LER of the dielectric lines is investigated as a function of the dielectric material, the trench depth, and the stress in the sacrificial hard mask. Finally, we elaborate on the different options to enable scaling down from 24 nm MP to 16 nm MP, and demonstrate 8 nm line/space gratings with 193i-based SAOP.
In this work, we present and compare two integration approaches to enable self-alignment of the block suitable for the 5- nm technology node. The first approach is exploring the insertion of a spin-on metal-based material to memorize the first block and act as an etch stop layer in the overall integration. The second approach is evaluating the self-aligned block technology employing widely used organic materials and well-known processes. The concept and the motivation are discussed considering the effects on design and mask count as well as the impact on process complexity and EPE budget. We show the integration schemes and discuss the requirements to enable self-alignment. We present the details of materials and processes selection to allow optimal selective etches and we demonstrate the proof of concept using a 16- nm half-pitch BEOL vehicle. Finally, a study on technology insertion and cost estimation is presented.
In this work, we explore the performances of a low-temperature PEALD technology used to trim/clean/smooth and reshape ArF photoresist lines that could subsequently receive an in-situ spacer deposition required to build up any SAxP grating. Different gas mixtures (O2, N2, H2, Ar and combinations) are evaluated on both blanket and patterned wafers. Trim rate, line profile, surface roughness and chemical modification are characterized using ellipsometry, Fourier transform infrared spectroscopy and atomic force microscopy. The photoresist line roughness is measured from top down SEM imaging and the different contributors to the roughness determined from a Power Spectral Density (PSD) analysis. Few results obtained on EUV photoresist blanket wafers using similar plasma treatments will also be briefly presented.
Proc. SPIE. 10143, Extreme Ultraviolet (EUV) Lithography VIII
KEYWORDS: Lithography, Logic, Optical lithography, Etching, Metals, Photomasks, Extreme ultraviolet, Extreme ultraviolet lithography, Double patterning technology, Critical dimension metrology, Semiconducting wafers, Stochastic processes, System on a chip, Back end of line
The imec N7 (iN7) platform has been developed to evaluate EUV patterning of advanced logic BEOL layers. Its design is based on a 42 nm first-level metal (M1) pitch, and a 32 nm pitch for the subsequent M2 layer. With these pitches, the iN7 node is an ‘aggressive’ full-scaled N7, corresponding to IDM N7, or foundry N5.
Even in a 1D design style, single exposure of the 16 nm half-pitch M2 layer is very challenging for EUV lithography, because of its tight tip-to-tip configurations. Therefore, the industry is considering the hybrid use of ArFi-based SAQP combined with EUV Block as an alternative to EUV single exposure. As a consequence, the EUV Block layer may be one of the first layers to adopt EUV lithography in HVM.
In this paper, we report on the imec iN7 SAQP + Block litho performance and process integration, targeting the M2 patterning for a 7.5 track logic design. The Block layer is exposed on an ASML NXE:3300 EUV-scanner at imec, using optimized illumination conditions and state-of-the-art metal-containing negative tone resist (Inpria). Subsequently, the SAQP and block structures are characterized in a morphological study, assessing pattern fidelity and CD/EPE variability. The work is an experimental feasibility study of EUV insertion, for SAQP + Block M2 patterning on an industry-relevant N5 use-case.
Modifying the properties of ZnO by means of incorporating antimony, arsenic or phosphorus impurities is of interest
since these group V elements have been reported in the literature among the few successful p-type dopants in this
technologically promising II-VI compound. The lattice location of ion-implanted Sb, As, and P in ZnO single crystals
was investigated by means of the electron emission channeling technique using the radioactive isotopes 124Sb, 73As and
33P and it is found that they preferentially occupy substitutional Zn sites while the possible fractions on substitutional O
sites are a few percent at maximum. The lattice site preference is understandable from the relatively large ionic size of
the heavy mass group V elements. Unfortunately the presented results cannot finally settle the interesting issue whether
substitutional Sb, As or P on oxygen sites or SbZn-2VZn, AsZn-2VZn or PZn-2VZn complexes (as suggested in the
literature) are responsible for the acceptor action. However, the fact that the implanted group V ions prefer the
substitutional Zn sites is clearly a strong argument in favour of the complex acceptor model, while it discourages the
notion that Sb, As and P act as simple "chemical" acceptors in ZnO.