CAD based recipe creation paves the way for complete recipe automation and minimizes the need for human
intervention. A high volume production environment presents its own unique challenges for automatic CAD based
metrology. In our work we describe the approach of automatic offline CD-SEM recipe creation for production using the
Applied Materials OPC Check application. In addition, the study includes a comprehensive analysis of success rates for
recipe creation, pattern recognition and measurement. The stability of automatically created recipes was evaluated
against process variations for a number of test structures which are typically used for production control. Data was
collected for various layers on multiple lots and the performance was compared to that of recipes created directly on the
All offline recipes for production were generated waferless from design data with success rates of 100%. They showed
pattern recognition success rates and measurement success rates at the same level or better than the rates typically
reached by recipes created directly on the tool by an experienced CD-SEM engineer.
The volume of measurements and the complexity of metrology recipes in state-of-the-art semiconductor manufacturing
have made the conventional manual process of creating the recipes increasingly problematic. To address these
challenges, we implemented a system for automatically creating production metrology recipes. We present results from
the use of this system for CD-SEM and overlay tools in a high-volume manufacturing environment and show that, in
addition to the benefits of reduced engineering time and improved tool utilization, recipes produced by the automated
system are in many respects more robust than the equivalent manually created recipes.
Overlay process control up to and including the 45nm node has been implemented using a small number of large
measurement targets placed in the scribe lines surrounding each field. There is increasing concern that this scheme does
not provide sufficiently accurate information about the variation of overlay within the product area of the device.
These concerns have led to the development of new, smaller targets designed for inclusion within the device area of real
products [1,2]. The targets can be as small as 1-3μm on a side, which is small enough to permit their inclusion inside the
device pattern of many products. They are measured using a standard optical overlay tool, and then calibrated. However,
there is a tradeoff between total measurement uncertainty (TMU) and target size reduction . Also the calibration
scheme applied impacts TMU.
We report results from measurements of 3μm targets on 45nm production wafers at both develop and etch stages. An
advantage of these small targets is that at the etch stage they can readily be measured using a SEM, which provides a
method for verifying the accuracy of the measurements.
We show how the 3μm in-chip targets can be used to obtain detailed information for in-device overlay variability and to
maintain overlay control in successive process generations.