After the introduction of multi-patterning techniques like multiple Litho-Etch (LEn ) steps and/or Spacer Assisted Double/Quadruple Patterning (SADP/SAQP), the amount of masks required to produce a semiconductor device has increased significantly. The main reason was that a functional layer could no longer be exposed in one single litho step due to the elevated pitch requirements. Consequently, the required pattern had to be split-up and divided over multiple masks. One can imagine that this has put a huge constraint on the mask-to-mask on-product overlay requirements and control. It was already shown before that for the LE2 use-case the mask-to-mask contribution is the second largest contributor (after the scanner) to the overall on-product overlay. In order to keep the on-product overlay within specification over time, the number of on-wafer overlay metrology steps inside the fab increased even more. Since more masks are used per layer, multiple combinations are now possible to measure and control both the intra-layer as well as the inter-layer overlay. As a consequence, the increasing number of metrology steps has resulted in a negative impact on the overall wafer/lot cycle time in the fab. It would be beneficial to fully characterize the mask-to-mask overlay off-line and apply computational overlay techniques to compute the on-wafer overlay. This enables smart metrology sampling to address and reduce the overall wafer/lot cycle time inside the fab. In this work, we performed a correlation study between off-line mask-to-mask registration metrology and on-wafer measurements. The off-line overlay measurements were performed on a PROVE® tool while the exposures and scanner readouts were executed on an ASML TWINSCAN™. Two ASML qualification (BaseLiner) masks were used for this purpose. Extensive off-line registration measurements were performed on both reticles including the reticle alignment marks as well as the image field metrology features (gratings). We show an excellent correlation between the measurements on the PROVE® tool and the on-wafer results reaching R2 < 0.96 with an accuracy of 0.58-nm. The accuracy is determined by the reticle alignment accuracy on the scanner and the quality of the masks. We have identified the underlying contributors to the error budget to enable a further improvement of the correlation between the mask-tomask and the on-wafer overlay. Since the results of this first investigation were so promising, the effect of a pellicle mounted on one of the masks was studied as well. The off-line mask-to-mask registration metrology was repeated and the resulting computational overlay has been compared with the on-wafer results.
Next-generation lithography based on EUV continues to move forward to high-volume manufacturing. Given the
technical challenges and the throughput concerns a hybrid approach with 193 nm immersion lithography is expected, at
least in the initial state. Due to the increasing complexity at smaller nodes a multitude of different masks, both DUV
(193 nm) and EUV (13.5 nm) reticles, will then be required in the lithography process-flow. The individual registration
of each mask and the resulting overlay error are of crucial importance in order to ensure proper functionality of the chips.
While registration and overlay metrology on DUV masks has been the standard for decades, this has yet to be
demonstrated on EUV masks. Past generations of mask registration tools were not necessarily limited in their tool
stability, but in their resolution capabilities. The scope of this work is an image placement investigation of high-end
EUV masks together with a registration and resolution performance qualification. For this we employ a new generation
registration metrology system embedded in a production environment for full-spec EUV masks. This paper presents
excellent registration performance not only on standard overlay markers but also on more sophisticated e-beam
Improving wafer On Product Overlay (OPO) is becoming a major challenge in lithography, especially for multipatterning techniques like N-repetitive Litho-Etch steps (LEN, N ≥ 2). When using different scanner settings and litho processes between inter-layer overlays, intra-field overlay control becomes more complicated. In addition to the Image Placement Error (IPE) contribution, the TWINSCANTM lens fingerprint in combination with the exposure settings is playing a significant role as well. Furthermore the scanner needs to deal with dynamic fingerprints caused by for instance lens and/or reticle heating.
This paper will demonstrate the complementary RegC® and TWINSCANTM solution for improving the OPO by cooptimizing the correction capabilities of the individual tools, respectively. As a consequence, the systematic intra-field fingerprints can be decreased along with the overlay (OVL) error at wafer level. Furthermore, the application could be utilized for extending some of the scanner actuators ranges by inducing a pre-determined signatures. These solutions perfectly fit into the ASML Litho InSight (LIS) product in which feedforward and feedback corrections based on YieldStar overlay and other measurements are used to improve the OPO. While the TWINSCANTM scanner corrects for global distortions (up to third order) - scanner Correctable Errors ( CE), the RegC® application can correct for the None Correctable Errors (NCE) by making the high frequency NCE into a CE with low frequency nature. The RegC® induces predictable deformation elements inside the quartz (Qz) material of the reticle, and by doing so it can induce a desired pre-defined signature into the reticle. The deformation introduced by the RegC® is optimized for the actual wafer print taking into account the scale and ortho compensation by the scanner, to correct for the systematic fingerprints and the wafer overlay. These two applications might be very powerful and could contribute to achieve a better OPO performance.
With the introduction of complex lithography schemes like double and multi – patterning and new design principles like
gridded designs with cut masks the requirements for mask to mask overlay have increased dramatically. Still, there are
some good news too for the mask industry since more mask are needed and qualified. Although always confronted with
throughput demands, latest writing tool developments are able to keep pace with ever increasing pattern placement specs
not only for global signatures but for in-die features within the active area. Placement specs less than 3nm (max. 3
Sigma) are expected and needed in all cases in order to keep the mask contribution to the overall overlay budget at an
accepted level. The qualification of these masks relies on high precision metrology tools which have to fulfill stringent
metrology as well as resolution constrains at the same time.
Furthermore, multi-patterning and gridded designs with pinhole type cut masks are drivers for a paradigm shift in
registration metrology from classical registration crosses to in-die registration metrology on production features. These
requirements result in several challenges for registration metrology tools. The resolution of the system must be
sufficiently high to resolve small production features. At the same time tighter repeatability is required. Furthermore,
tool induced shift (TIS) limit the accuracy of in-die measurements.
This paper discusses and demonstrates the importance of low illumination wavelength together with low aberrations for
best contrast imaging for in-die registration metrology. Typical effects like tool induced shift are analyzed and evaluated
using the ZEISS PROVE® registration metrology tool. Additionally, we will address performance gains when going to
higher resolution. The direct impact on repeatability for small features by registration measurements will be discussed as